Network Resynthesis Algorithms for Delay Minimization

Kuang-Chien CHEN; Masahiro FUJITA

Network Resynthesis Algorithms for Delay Minimization

Kuang-Chien CHEN, Masahiro FUJITA

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Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed_up algorithm in SIS-1.0 are presented.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.9 pp.1102-1113

Publication Date: 1993/09/25

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Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: Logic Synthesis

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Kuang-Chien CHEN, Masahiro FUJITA, "Network Resynthesis Algorithms for Delay Minimization" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 9, pp. 1102-1113, September 1993, doi: .
Abstract: Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed_up algorithm in SIS-1.0 are presented.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_9_1102/_p

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@ARTICLE{e76-d_9_1102,
author={Kuang-Chien CHEN, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Information},
title={Network Resynthesis Algorithms for Delay Minimization},
year={1993},
volume={E76-D},
number={9},
pages={1102-1113},
abstract={Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed_up algorithm in SIS-1.0 are presented.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Network Resynthesis Algorithms for Delay Minimization
T2 - IEICE TRANSACTIONS on Information
SP - 1102
EP - 1113
AU - Kuang-Chien CHEN
AU - Masahiro FUJITA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1993
AB - Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed_up algorithm in SIS-1.0 are presented.
ER -