Automatic Hardware Synthesis of Multimedia Synchronizers from High-Level Specifications
Summary :
In this paper, we show that by suitably selecting a notation to construct synchronization requirement specifications (SRS) for multimedia presentation we can express the timing characteristics at an abstract level, verify the specification, and obtain a hardware implementation through a sequence of transformations of the specification. First, we introduce the notion of a well-formed SRS and its hardware model. Second, we model an SRS as a timed Petri net and interpret the transitions of the net as hardware signals. To obtain logic functions from the SRS, we simplify the net and obtain a signal transition graph satisfying the unique state coding property. Finally, we show how to obtain a logic-level design of synchronizers.
- Publication
- IEICE TRANSACTIONS on Information Vol.E79-D No.6 pp.743-751
- Publication Date
- 1996/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Multimedia Computing and Communications)
- Category
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Kshirasagar NAIK, "Automatic Hardware Synthesis of Multimedia Synchronizers from High-Level Specifications" in IEICE TRANSACTIONS on Information,
vol. E79-D, no. 6, pp. 743-751, June 1996, doi: .
Abstract: In this paper, we show that by suitably selecting a notation to construct synchronization requirement specifications (SRS) for multimedia presentation we can express the timing characteristics at an abstract level, verify the specification, and obtain a hardware implementation through a sequence of transformations of the specification. First, we introduce the notion of a well-formed SRS and its hardware model. Second, we model an SRS as a timed Petri net and interpret the transitions of the net as hardware signals. To obtain logic functions from the SRS, we simplify the net and obtain a signal transition graph satisfying the unique state coding property. Finally, we show how to obtain a logic-level design of synchronizers.
URL: https://global.ieice.org/en_transactions/information/10.1587/e79-d_6_743/_p
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@ARTICLE{e79-d_6_743,
author={Kshirasagar NAIK, },
journal={IEICE TRANSACTIONS on Information},
title={Automatic Hardware Synthesis of Multimedia Synchronizers from High-Level Specifications},
year={1996},
volume={E79-D},
number={6},
pages={743-751},
abstract={In this paper, we show that by suitably selecting a notation to construct synchronization requirement specifications (SRS) for multimedia presentation we can express the timing characteristics at an abstract level, verify the specification, and obtain a hardware implementation through a sequence of transformations of the specification. First, we introduce the notion of a well-formed SRS and its hardware model. Second, we model an SRS as a timed Petri net and interpret the transitions of the net as hardware signals. To obtain logic functions from the SRS, we simplify the net and obtain a signal transition graph satisfying the unique state coding property. Finally, we show how to obtain a logic-level design of synchronizers.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Automatic Hardware Synthesis of Multimedia Synchronizers from High-Level Specifications
T2 - IEICE TRANSACTIONS on Information
SP - 743
EP - 751
AU - Kshirasagar NAIK
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E79-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 1996
AB - In this paper, we show that by suitably selecting a notation to construct synchronization requirement specifications (SRS) for multimedia presentation we can express the timing characteristics at an abstract level, verify the specification, and obtain a hardware implementation through a sequence of transformations of the specification. First, we introduce the notion of a well-formed SRS and its hardware model. Second, we model an SRS as a timed Petri net and interpret the transitions of the net as hardware signals. To obtain logic functions from the SRS, we simplify the net and obtain a signal transition graph satisfying the unique state coding property. Finally, we show how to obtain a logic-level design of synchronizers.
ER -
English
