IEICE TRANSACTIONS on Information
Message-Based Efficient Remote Memory Access on a Highly Parallel Computer EM-X
Summary :
Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.
- Publication
- IEICE TRANSACTIONS on Information Vol.E79-D No.8 pp.1065-1071
- Publication Date
- 1996/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
- Category
- Architectures
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Yuetsu KODAMA, Hirohumi SAKANE, Mitsuhisa SATO, Hayato YAMANA, Shuichi SAKAI, Yoshinori YAMAGUCHI, "Message-Based Efficient Remote Memory Access on a Highly Parallel Computer EM-X" in IEICE TRANSACTIONS on Information,
vol. E79-D, no. 8, pp. 1065-1071, August 1996, doi: .
Abstract: Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.
URL: https://global.ieice.org/en_transactions/information/10.1587/e79-d_8_1065/_p
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@ARTICLE{e79-d_8_1065,
author={Yuetsu KODAMA, Hirohumi SAKANE, Mitsuhisa SATO, Hayato YAMANA, Shuichi SAKAI, Yoshinori YAMAGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Message-Based Efficient Remote Memory Access on a Highly Parallel Computer EM-X},
year={1996},
volume={E79-D},
number={8},
pages={1065-1071},
abstract={Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Message-Based Efficient Remote Memory Access on a Highly Parallel Computer EM-X
T2 - IEICE TRANSACTIONS on Information
SP - 1065
EP - 1071
AU - Yuetsu KODAMA
AU - Hirohumi SAKANE
AU - Mitsuhisa SATO
AU - Hayato YAMANA
AU - Shuichi SAKAI
AU - Yoshinori YAMAGUCHI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E79-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 1996
AB - Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.
ER -
English
