IEICE TRANSACTIONS on Information
Fast Scheduling and Allocation Algorithms for Entropy CODEC
Summary :
Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.10 pp.982-992
- Publication Date
- 1997/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
- Category
- High Level Synthesis
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Katsuharu SUZUKI, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, "Fast Scheduling and Allocation Algorithms for Entropy CODEC" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 10, pp. 982-992, October 1997, doi: .
Abstract: Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_10_982/_p
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@ARTICLE{e80-d_10_982,
author={Katsuharu SUZUKI, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Information},
title={Fast Scheduling and Allocation Algorithms for Entropy CODEC},
year={1997},
volume={E80-D},
number={10},
pages={982-992},
abstract={Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Fast Scheduling and Allocation Algorithms for Entropy CODEC
T2 - IEICE TRANSACTIONS on Information
SP - 982
EP - 992
AU - Katsuharu SUZUKI
AU - Nozomu TOGAWA
AU - Masao SATO
AU - Tatsuo OHTSUKI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1997
AB - Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.
ER -
English
