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Vijay K. JAIN, Tadasse GHIRMAI, Susumu HORIGUCHI, "TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 9, pp. 837-846, September 1997, doi: .
Abstract: Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_9_837/_p
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@ARTICLE{e80-d_9_837,
author={Vijay K. JAIN, Tadasse GHIRMAI, Susumu HORIGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing},
year={1997},
volume={E80-D},
number={9},
pages={837-846},
abstract={Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing
T2 - IEICE TRANSACTIONS on Information
SP - 837
EP - 846
AU - Vijay K. JAIN
AU - Tadasse GHIRMAI
AU - Susumu HORIGUCHI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1997
AB - Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.
ER -