IEICE TRANSACTIONS on Information
Fault-Tolerant Meshes with Efficient Layouts
Summary :
This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(
- Publication
- IEICE TRANSACTIONS on Information Vol.E81-D No.1 pp.56-65
- Publication Date
- 1998/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Fault Tolerant Computing
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Toshinori YAMADA, Shuichi UENO, "Fault-Tolerant Meshes with Efficient Layouts" in IEICE TRANSACTIONS on Information,
vol. E81-D, no. 1, pp. 56-65, January 1998, doi: .
Abstract: This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(
URL: https://global.ieice.org/en_transactions/information/10.1587/e81-d_1_56/_p
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@ARTICLE{e81-d_1_56,
author={Toshinori YAMADA, Shuichi UENO, },
journal={IEICE TRANSACTIONS on Information},
title={Fault-Tolerant Meshes with Efficient Layouts},
year={1998},
volume={E81-D},
number={1},
pages={56-65},
abstract={This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - Fault-Tolerant Meshes with Efficient Layouts
T2 - IEICE TRANSACTIONS on Information
SP - 56
EP - 65
AU - Toshinori YAMADA
AU - Shuichi UENO
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E81-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 1998
AB - This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(
ER -
English
