Crossbar Arbiter Architecture for High-Speed MAPOS Switch
Summary :
This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulation-based performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware.
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- IEICE TRANSACTIONS on Information Vol.E83-D No.5 pp.1028-1038
- Publication Date
- 2000/05/25
- Publicized
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- Type of Manuscript
- Special Section PAPER (Special Issue on Next Generation Internet Technologies and Their Applications)
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Tsuyoshi OGURA, Satoru YAGI, Tetsuo KAWANO, Mitsuru MARUYAMA, Naohisa TAKAHASHI, "Crossbar Arbiter Architecture for High-Speed MAPOS Switch" in IEICE TRANSACTIONS on Information,
vol. E83-D, no. 5, pp. 1028-1038, May 2000, doi: .
Abstract: This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulation-based performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware.
URL: https://global.ieice.org/en_transactions/information/10.1587/e83-d_5_1028/_p
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@ARTICLE{e83-d_5_1028,
author={Tsuyoshi OGURA, Satoru YAGI, Tetsuo KAWANO, Mitsuru MARUYAMA, Naohisa TAKAHASHI, },
journal={IEICE TRANSACTIONS on Information},
title={Crossbar Arbiter Architecture for High-Speed MAPOS Switch},
year={2000},
volume={E83-D},
number={5},
pages={1028-1038},
abstract={This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulation-based performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Crossbar Arbiter Architecture for High-Speed MAPOS Switch
T2 - IEICE TRANSACTIONS on Information
SP - 1028
EP - 1038
AU - Tsuyoshi OGURA
AU - Satoru YAGI
AU - Tetsuo KAWANO
AU - Mitsuru MARUYAMA
AU - Naohisa TAKAHASHI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E83-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2000
AB - This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulation-based performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware.
ER -
English
