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Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.

- Publication
- IEICE TRANSACTIONS on Information Vol.E84-D No.11 pp.1476-1485

- Publication Date
- 2001/11/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- Special Section PAPER (Special Issue on Function Integrated Information Systems)

- Category

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Xiaohong JIANG, Susumu HORIGUCHI, "Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 11, pp. 1476-1485, November 2001, doi: .

Abstract: Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.

URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_11_1476/_p

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@ARTICLE{e84-d_11_1476,

author={Xiaohong JIANG, Susumu HORIGUCHI, },

journal={IEICE TRANSACTIONS on Information},

title={Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network},

year={2001},

volume={E84-D},

number={11},

pages={1476-1485},

abstract={Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.},

keywords={},

doi={},

ISSN={},

month={November},}

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TY - JOUR

TI - Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network

T2 - IEICE TRANSACTIONS on Information

SP - 1476

EP - 1485

AU - Xiaohong JIANG

AU - Susumu HORIGUCHI

PY - 2001

DO -

JO - IEICE TRANSACTIONS on Information

SN -

VL - E84-D

IS - 11

JA - IEICE TRANSACTIONS on Information

Y1 - November 2001

AB - Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.

ER -