Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme

Woo-Chan PARK; Cheol-Ho JEONG; Tack-Don HAN

Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme

Woo-Chan PARK, Cheol-Ho JEONG, Tack-Don HAN

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The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.

Publication: IEICE TRANSACTIONS on Information Vol.E85-D No.8 pp.1341-1345

Publication Date: 2002/08/01

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Type of Manuscript: LETTER

Category: Computer System Element

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Woo-Chan PARK, Cheol-Ho JEONG, Tack-Don HAN, "Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme" in IEICE TRANSACTIONS on Information, vol. E85-D, no. 8, pp. 1341-1345, August 2002, doi: .
Abstract: The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_8_1341/_p

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@ARTICLE{e85-d_8_1341,
author={Woo-Chan PARK, Cheol-Ho JEONG, Tack-Don HAN, },
journal={IEICE TRANSACTIONS on Information},
title={Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme},
year={2002},
volume={E85-D},
number={8},
pages={1341-1345},
abstract={The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - Design of the Floating-Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme
T2 - IEICE TRANSACTIONS on Information
SP - 1341
EP - 1345
AU - Woo-Chan PARK
AU - Cheol-Ho JEONG
AU - Tack-Don HAN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2002
AB - The format conversion operations between a floating-point number and an integer number and a round operation are the important standard floating-point operations. In most cases, these operations are implemented by adding additional hardware to the floating-point adder. The SR (simultaneous rounding) method, one of the techniques used to improve the performance of the floating-point adder, can perform addition and rounding operations at the same stage and is an efficient method with respect to the silicon area and its performance. In this paper, a hardware model to execute CRops (conversion and rounding operations) for the SR floating-point adder is presented and CRops are analyzed on the proposed hardware model. Implementation details are also discussed. The proposed scheme can maintain the advantages of the SR method and can perform each CRop with three pipeline stages.
ER -