An Image Retrieval System Using FPGAs

Koji NAKANO; Etsuko TAKAMICHI

An Image Retrieval System Using FPGAs

Koji NAKANO, Etsuko TAKAMICHI

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The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of images I₁, I₂,, our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether I_i has a similar subimage to T for any image I_i and a particular template T. The created Verilog HDL source is compiled and embedded in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a timing analyzer. Since the generated hardware attains up to 3000 speed-up factor over the software solution, our approach is promising.

Publication: IEICE TRANSACTIONS on Information Vol.E86-D No.5 pp.811-818

Publication Date: 2003/05/01

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Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing)

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Koji NAKANO, Etsuko TAKAMICHI, "An Image Retrieval System Using FPGAs" in IEICE TRANSACTIONS on Information, vol. E86-D, no. 5, pp. 811-818, May 2003, doi: .
Abstract: The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of images I₁, I₂,, our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether I_i has a similar subimage to T for any image I_i and a particular template T. The created Verilog HDL source is compiled and embedded in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a timing analyzer. Since the generated hardware attains up to 3000 speed-up factor over the software solution, our approach is promising.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_5_811/_p

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@ARTICLE{e86-d_5_811,
author={Koji NAKANO, Etsuko TAKAMICHI, },
journal={IEICE TRANSACTIONS on Information},
title={An Image Retrieval System Using FPGAs},
year={2003},
volume={E86-D},
number={5},
pages={811-818},
abstract={The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of images I₁, I₂,, our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether I_i has a similar subimage to T for any image I_i and a particular template T. The created Verilog HDL source is compiled and embedded in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a timing analyzer. Since the generated hardware attains up to 3000 speed-up factor over the software solution, our approach is promising.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - An Image Retrieval System Using FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 811
EP - 818
AU - Koji NAKANO
AU - Etsuko TAKAMICHI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2003
AB - The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of images I₁, I₂,, our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether I_i has a similar subimage to T for any image I_i and a particular template T. The created Verilog HDL source is compiled and embedded in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a timing analyzer. Since the generated hardware attains up to 3000 speed-up factor over the software solution, our approach is promising.
ER -