IEICE TRANSACTIONS on Information
Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions
Summary :
This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.
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- IEICE TRANSACTIONS on Information Vol.E87-D No.3 pp.637-641
- Publication Date
- 2004/03/01
- Publicized
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- Type of Manuscript
- Special Section LETTER (Special Section on Test and Verification of VLSI)
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Kiyoharu HAMAGUCHI, "Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions" in IEICE TRANSACTIONS on Information,
vol. E87-D, no. 3, pp. 637-641, March 2004, doi: .
Abstract: This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.
URL: https://global.ieice.org/en_transactions/information/10.1587/e87-d_3_637/_p
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@ARTICLE{e87-d_3_637,
author={Kiyoharu HAMAGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions},
year={2004},
volume={E87-D},
number={3},
pages={637-641},
abstract={This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions
T2 - IEICE TRANSACTIONS on Information
SP - 637
EP - 641
AU - Kiyoharu HAMAGUCHI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E87-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2004
AB - This letter handles symbolic simulation for high-level hardware design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics.
ER -
English
