An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC
Summary :
In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.
- Publication
- IEICE TRANSACTIONS on Information Vol.E90-D No.1 pp.99-107
- Publication Date
- 2007/01/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Image Technology)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Chung-Ming CHEN, Chung-Ho CHEN, "An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 1, pp. 99-107, January 2007, doi: .
Abstract: In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.
URL: https://global.ieice.org/en_transactions/information/10.1587/e90-d_1_99/_p
Copy
@ARTICLE{e90-d_1_99,
author={Chung-Ming CHEN, Chung-Ho CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC},
year={2007},
volume={E90-D},
number={1},
pages={99-107},
abstract={In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.},
keywords={},
doi={},
ISSN={1745-1361},
month={January},}
Copy
TY - JOUR
TI - An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC
T2 - IEICE TRANSACTIONS on Information
SP - 99
EP - 107
AU - Chung-Ming CHEN
AU - Chung-Ho CHEN
PY - 2007
DO -
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2007
AB - In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.
ER -
English
