Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations
Summary :
This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG representation to describe GFs defined by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description of the multipliers in a hierarchical manner and show that the verification time can be greatly reduced in comparison with those of the conventional techniques. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and an inversion circuit over composite field GF(((22)2)2) in order to demonstrate the advantages of normal-basis circuits over polynomial-basis ones.
- Publication
- IEICE TRANSACTIONS on Information Vol.E97-D No.9 pp.2270-2277
- Publication Date
- 2014/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2013LOP0012
- Type of Manuscript
- Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
- Category
- VLSI Architecture
Authors
Kotaro OKAMOTO
Tohoku University
Naofumi HOMMA
Tohoku University
Takafumi AOKI
Tohoku University
Keyword
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Kotaro OKAMOTO, Naofumi HOMMA, Takafumi AOKI, "Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations" in IEICE TRANSACTIONS on Information,
vol. E97-D, no. 9, pp. 2270-2277, September 2014, doi: 10.1587/transinf.2013LOP0012.
Abstract: This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG representation to describe GFs defined by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description of the multipliers in a hierarchical manner and show that the verification time can be greatly reduced in comparison with those of the conventional techniques. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and an inversion circuit over composite field GF(((22)2)2) in order to demonstrate the advantages of normal-basis circuits over polynomial-basis ones.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2013LOP0012/_p
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@ARTICLE{e97-d_9_2270,
author={Kotaro OKAMOTO, Naofumi HOMMA, Takafumi AOKI, },
journal={IEICE TRANSACTIONS on Information},
title={Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations},
year={2014},
volume={E97-D},
number={9},
pages={2270-2277},
abstract={This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG representation to describe GFs defined by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description of the multipliers in a hierarchical manner and show that the verification time can be greatly reduced in comparison with those of the conventional techniques. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and an inversion circuit over composite field GF(((22)2)2) in order to demonstrate the advantages of normal-basis circuits over polynomial-basis ones.},
keywords={},
doi={10.1587/transinf.2013LOP0012},
ISSN={1745-1361},
month={September},}
Copy
TY - JOUR
TI - Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations
T2 - IEICE TRANSACTIONS on Information
SP - 2270
EP - 2277
AU - Kotaro OKAMOTO
AU - Naofumi HOMMA
AU - Takafumi AOKI
PY - 2014
DO - 10.1587/transinf.2013LOP0012
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2014
AB - This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG representation to describe GFs defined by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description of the multipliers in a hierarchical manner and show that the verification time can be greatly reduced in comparison with those of the conventional techniques. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and an inversion circuit over composite field GF(((22)2)2) in order to demonstrate the advantages of normal-basis circuits over polynomial-basis ones.
ER -
English
