IEICE TRANSACTIONS on Information
A Multidimensional Configurable Processor Array — Vocalise
Summary :
A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.
- Publication
- IEICE TRANSACTIONS on Information Vol.E98-D No.2 pp.313-324
- Publication Date
- 2015/02/01
- Publicized
- 2014/10/27
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2014EDP7219
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Jiang LI
Tokyo University of Agriculture and Technology
Yusuke ATSUMARI
Tokyo University of Agriculture and Technology
Hiromasa KUBO
Tokyo University of Agriculture and Technology
Yuichi OGISHIMA
Tokyo University of Agriculture and Technology
Satoru YOKOTA
Tokyo University of Agriculture and Technology
Hakaru TAMUKOH
Kyushu Institute of Technology
Masatoshi SEKINE
Tokyo University of Agriculture and Technology
Keyword
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Jiang LI, Yusuke ATSUMARI, Hiromasa KUBO, Yuichi OGISHIMA, Satoru YOKOTA, Hakaru TAMUKOH, Masatoshi SEKINE, "A Multidimensional Configurable Processor Array — Vocalise" in IEICE TRANSACTIONS on Information,
vol. E98-D, no. 2, pp. 313-324, February 2015, doi: 10.1587/transinf.2014EDP7219.
Abstract: A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014EDP7219/_p
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@ARTICLE{e98-d_2_313,
author={Jiang LI, Yusuke ATSUMARI, Hiromasa KUBO, Yuichi OGISHIMA, Satoru YOKOTA, Hakaru TAMUKOH, Masatoshi SEKINE, },
journal={IEICE TRANSACTIONS on Information},
title={A Multidimensional Configurable Processor Array — Vocalise},
year={2015},
volume={E98-D},
number={2},
pages={313-324},
abstract={A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.},
keywords={},
doi={10.1587/transinf.2014EDP7219},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - A Multidimensional Configurable Processor Array — Vocalise
T2 - IEICE TRANSACTIONS on Information
SP - 313
EP - 324
AU - Jiang LI
AU - Yusuke ATSUMARI
AU - Hiromasa KUBO
AU - Yuichi OGISHIMA
AU - Satoru YOKOTA
AU - Hakaru TAMUKOH
AU - Masatoshi SEKINE
PY - 2015
DO - 10.1587/transinf.2014EDP7219
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2015
AB - A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.
ER -
English
