FPGA Hardware with Target-Reconfigurable Object Detector

Yoshifumi YAZAWA; Tsutomu YOSHIMI; Teruyasu TSUZUKI; Tomomi DOHI; Yuji YAMAUCHI; Takayoshi YAMASHITA; Hironobu FUJIYOSHI

doi:10.1587/transinf.2014OPP0008

FPGA Hardware with Target-Reconfigurable Object Detector

Yoshifumi YAZAWA, Tsutomu YOSHIMI, Teruyasu TSUZUKI, Tomomi DOHI, Yuji YAMAUCHI, Takayoshi YAMASHITA, Hironobu FUJIYOSHI

Full Text Views

0

Cite this

Summary :

Much effort has been applied to research on object detection by statistical learning methods in recent years, and the results of that work are expected to find use in fields such as ITS and security. Up to now, the research has included optimization of computational algorithms for real-time processing on hardware such as GPU's and FPGAs. Such optimization most often works only with particular parameters, which often forfeits the flexibility that comes with dynamic changing of the target object. We propose a hardware architecture for faster detection and flexible target reconfiguration while maintaining detection accuracy. Tests confirm operation in a practical time when implemented in an FPGA board.

Publication: IEICE TRANSACTIONS on Information Vol.E98-D No.9 pp.1637-1645

Publication Date: 2015/09/01

Publicized: 2015/06/22

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2014OPP0008

Type of Manuscript: Special Section PAPER (Special Section on Optimization and Learning Algorithms of Small Embedded Devices and Related Software/Hardware Implementation)

Category

Authors

Yoshifumi YAZAWA
  SANEI HYTECHS Co., Ltd.
Tsutomu YOSHIMI
  SANEI HYTECHS Co., Ltd.
Teruyasu TSUZUKI
  SANEI HYTECHS Co., Ltd.
Tomomi DOHI
  SANEI HYTECHS Co., Ltd.
Yuji YAMAUCHI
  Chubu University
Takayoshi YAMASHITA
  Chubu University
Hironobu FUJIYOSHI
  Chubu University

Keyword

dynamic reconfiguration of detection target, object detection, FPGA

Cite this

Copy

Yoshifumi YAZAWA, Tsutomu YOSHIMI, Teruyasu TSUZUKI, Tomomi DOHI, Yuji YAMAUCHI, Takayoshi YAMASHITA, Hironobu FUJIYOSHI, "FPGA Hardware with Target-Reconfigurable Object Detector" in IEICE TRANSACTIONS on Information, vol. E98-D, no. 9, pp. 1637-1645, September 2015, doi: 10.1587/transinf.2014OPP0008.
Abstract: Much effort has been applied to research on object detection by statistical learning methods in recent years, and the results of that work are expected to find use in fields such as ITS and security. Up to now, the research has included optimization of computational algorithms for real-time processing on hardware such as GPU's and FPGAs. Such optimization most often works only with particular parameters, which often forfeits the flexibility that comes with dynamic changing of the target object. We propose a hardware architecture for faster detection and flexible target reconfiguration while maintaining detection accuracy. Tests confirm operation in a practical time when implemented in an FPGA board.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014OPP0008/_p

Copy

@ARTICLE{e98-d_9_1637,
author={Yoshifumi YAZAWA, Tsutomu YOSHIMI, Teruyasu TSUZUKI, Tomomi DOHI, Yuji YAMAUCHI, Takayoshi YAMASHITA, Hironobu FUJIYOSHI, },
journal={IEICE TRANSACTIONS on Information},
title={FPGA Hardware with Target-Reconfigurable Object Detector},
year={2015},
volume={E98-D},
number={9},
pages={1637-1645},
abstract={Much effort has been applied to research on object detection by statistical learning methods in recent years, and the results of that work are expected to find use in fields such as ITS and security. Up to now, the research has included optimization of computational algorithms for real-time processing on hardware such as GPU's and FPGAs. Such optimization most often works only with particular parameters, which often forfeits the flexibility that comes with dynamic changing of the target object. We propose a hardware architecture for faster detection and flexible target reconfiguration while maintaining detection accuracy. Tests confirm operation in a practical time when implemented in an FPGA board.},
keywords={},
doi={10.1587/transinf.2014OPP0008},
ISSN={1745-1361},
month={September},}

Copy

TY - JOUR
TI - FPGA Hardware with Target-Reconfigurable Object Detector
T2 - IEICE TRANSACTIONS on Information
SP - 1637
EP - 1645
AU - Yoshifumi YAZAWA
AU - Tsutomu YOSHIMI
AU - Teruyasu TSUZUKI
AU - Tomomi DOHI
AU - Yuji YAMAUCHI
AU - Takayoshi YAMASHITA
AU - Hironobu FUJIYOSHI
PY - 2015
DO - 10.1587/transinf.2014OPP0008
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2015
AB - Much effort has been applied to research on object detection by statistical learning methods in recent years, and the results of that work are expected to find use in fields such as ITS and security. Up to now, the research has included optimization of computational algorithms for real-time processing on hardware such as GPU's and FPGAs. Such optimization most often works only with particular parameters, which often forfeits the flexibility that comes with dynamic changing of the target object. We propose a hardware architecture for faster detection and flexible target reconfiguration while maintaining detection accuracy. Tests confirm operation in a practical time when implemented in an FPGA board.
ER -