IEICE TRANSACTIONS on Information
Distributed Synchronization for Message-Passing Based Embedded Multiprocessors
Summary :
This paper presents a synchronization mechanism to effectively implement the lock and barrier protocols in a decentralized manner through explicit message passing. In the proposed solution, a simple and efficient synchronization control mechanism is proposed to support queued synchronization without contention. By using state-of-the-art Application-Specific Instruction-set Processor (ASIP) technology, we embed the synchronization functionality into a baseline processor, making the proposed mechanism feature ultra-low overhead. Experimental results show the proposed synchronization achieves ultra-low latency and almost ideal scalability when the number of processors increases.
- Publication
- IEICE TRANSACTIONS on Information Vol.E98-D No.2 pp.272-275
- Publication Date
- 2015/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2014RCL0001
- Type of Manuscript
- Special Section LETTER (Special Section on Reconfigurable Systems)
- Category
- Architecture
Authors
Hao XIAO
Nanjing University of Aeronautics and Astronautics
Ning WU
Nanjing University of Aeronautics and Astronautics
Fen GE
Nanjing University of Aeronautics and Astronautics
Guanyu ZHU
Shannon Lab
Lei ZHOU
Nanjing University of Aeronautics and Astronautics
Keyword
Latest Issue
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Hao XIAO, Ning WU, Fen GE, Guanyu ZHU, Lei ZHOU, "Distributed Synchronization for Message-Passing Based Embedded Multiprocessors" in IEICE TRANSACTIONS on Information,
vol. E98-D, no. 2, pp. 272-275, February 2015, doi: 10.1587/transinf.2014RCL0001.
Abstract: This paper presents a synchronization mechanism to effectively implement the lock and barrier protocols in a decentralized manner through explicit message passing. In the proposed solution, a simple and efficient synchronization control mechanism is proposed to support queued synchronization without contention. By using state-of-the-art Application-Specific Instruction-set Processor (ASIP) technology, we embed the synchronization functionality into a baseline processor, making the proposed mechanism feature ultra-low overhead. Experimental results show the proposed synchronization achieves ultra-low latency and almost ideal scalability when the number of processors increases.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014RCL0001/_p
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@ARTICLE{e98-d_2_272,
author={Hao XIAO, Ning WU, Fen GE, Guanyu ZHU, Lei ZHOU, },
journal={IEICE TRANSACTIONS on Information},
title={Distributed Synchronization for Message-Passing Based Embedded Multiprocessors},
year={2015},
volume={E98-D},
number={2},
pages={272-275},
abstract={This paper presents a synchronization mechanism to effectively implement the lock and barrier protocols in a decentralized manner through explicit message passing. In the proposed solution, a simple and efficient synchronization control mechanism is proposed to support queued synchronization without contention. By using state-of-the-art Application-Specific Instruction-set Processor (ASIP) technology, we embed the synchronization functionality into a baseline processor, making the proposed mechanism feature ultra-low overhead. Experimental results show the proposed synchronization achieves ultra-low latency and almost ideal scalability when the number of processors increases.},
keywords={},
doi={10.1587/transinf.2014RCL0001},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Distributed Synchronization for Message-Passing Based Embedded Multiprocessors
T2 - IEICE TRANSACTIONS on Information
SP - 272
EP - 275
AU - Hao XIAO
AU - Ning WU
AU - Fen GE
AU - Guanyu ZHU
AU - Lei ZHOU
PY - 2015
DO - 10.1587/transinf.2014RCL0001
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2015
AB - This paper presents a synchronization mechanism to effectively implement the lock and barrier protocols in a decentralized manner through explicit message passing. In the proposed solution, a simple and efficient synchronization control mechanism is proposed to support queued synchronization without contention. By using state-of-the-art Application-Specific Instruction-set Processor (ASIP) technology, we embed the synchronization functionality into a baseline processor, making the proposed mechanism feature ultra-low overhead. Experimental results show the proposed synchronization achieves ultra-low latency and almost ideal scalability when the number of processors increases.
ER -
English
