IEICE TRANSACTIONS on Information
Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD
Summary :
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.
- Publication
- IEICE TRANSACTIONS on Information Vol.E98-D No.2 pp.243-251
- Publication Date
- 2015/02/01
- Publicized
- 2014/11/19
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2014RCP0004
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Architecture
Authors
Bing XU
Tsinghua University
Shouyi YIN
Tsinghua University
Leibo LIU
Tsinghua University
Shaojun WEI
Tsinghua University
Keyword
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Bing XU, Shouyi YIN, Leibo LIU, Shaojun WEI, "Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD" in IEICE TRANSACTIONS on Information,
vol. E98-D, no. 2, pp. 243-251, February 2015, doi: 10.1587/transinf.2014RCP0004.
Abstract: Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014RCP0004/_p
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@ARTICLE{e98-d_2_243,
author={Bing XU, Shouyi YIN, Leibo LIU, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Information},
title={Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD},
year={2015},
volume={E98-D},
number={2},
pages={243-251},
abstract={Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.},
keywords={},
doi={10.1587/transinf.2014RCP0004},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD
T2 - IEICE TRANSACTIONS on Information
SP - 243
EP - 251
AU - Bing XU
AU - Shouyi YIN
AU - Leibo LIU
AU - Shaojun WEI
PY - 2015
DO - 10.1587/transinf.2014RCP0004
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2015
AB - Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.
ER -
English
