IEICE TRANSACTIONS on Information
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC
Summary :
In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for single-cycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance.
- Publication
- IEICE TRANSACTIONS on Information Vol.E98-D No.2 pp.252-261
- Publication Date
- 2015/02/01
- Publicized
- 2014/11/19
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2014RCP0009
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Architecture
Authors
Motoki AMAGASAKI
Kumamoto University
Qian ZHAO
Kumamoto University
Masahiro IIDA
Kumamoto University
Morihiro KUGA
Kumamoto University
Toshinori SUEYOSHI
Kumamoto University
Keyword
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Motoki AMAGASAKI, Qian ZHAO, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, "Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC" in IEICE TRANSACTIONS on Information,
vol. E98-D, no. 2, pp. 252-261, February 2015, doi: 10.1587/transinf.2014RCP0009.
Abstract: In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for single-cycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014RCP0009/_p
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@ARTICLE{e98-d_2_252,
author={Motoki AMAGASAKI, Qian ZHAO, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Information},
title={Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC},
year={2015},
volume={E98-D},
number={2},
pages={252-261},
abstract={In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for single-cycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance.},
keywords={},
doi={10.1587/transinf.2014RCP0009},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC
T2 - IEICE TRANSACTIONS on Information
SP - 252
EP - 261
AU - Motoki AMAGASAKI
AU - Qian ZHAO
AU - Masahiro IIDA
AU - Morihiro KUGA
AU - Toshinori SUEYOSHI
PY - 2015
DO - 10.1587/transinf.2014RCP0009
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2015
AB - In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for single-cycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance.
ER -
English
