IEICE TRANSACTIONS on Information
Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration
Summary :
In this paper, we discuss performance modeling of 3-D stencil computing on an FPGA accelerator with a high-level synthesis environment, aiming for efficient exploration of user-space design parameters. First, we analyze resource utilization and performance to formulate these relationships as mathematical models. Then, in order to evaluate our proposed models, we implement heat conduction simulations as a benchmark application, by using MaxCompiler, which is a high-level synthesis tool for FPGAs, and MaxGenFD, which is a domain specific framework of the MaxCompiler for finite-difference equation solvers. The experimental results with various settings of architectural design parameters show the best combination of design parameters for pipeline structure can be systematically found by using our models. The effects of changing arithmetic accuracy and using data stream compression are also discussed.
- Publication
- IEICE TRANSACTIONS on Information Vol.E98-D No.2 pp.298-308
- Publication Date
- 2015/02/01
- Publicized
- 2014/11/19
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2014RCP0013
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Application
Authors
Keisuke DOHI
Nagasaki University
Koji OKINA
Nagasaki University
Rie SOEJIMA
Nagasaki University
Yuichiro SHIBATA
Nagasaki University
Kiyoshi OGURI
Nagasaki University
Keyword
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Keisuke DOHI, Koji OKINA, Rie SOEJIMA, Yuichiro SHIBATA, Kiyoshi OGURI, "Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration" in IEICE TRANSACTIONS on Information,
vol. E98-D, no. 2, pp. 298-308, February 2015, doi: 10.1587/transinf.2014RCP0013.
Abstract: In this paper, we discuss performance modeling of 3-D stencil computing on an FPGA accelerator with a high-level synthesis environment, aiming for efficient exploration of user-space design parameters. First, we analyze resource utilization and performance to formulate these relationships as mathematical models. Then, in order to evaluate our proposed models, we implement heat conduction simulations as a benchmark application, by using MaxCompiler, which is a high-level synthesis tool for FPGAs, and MaxGenFD, which is a domain specific framework of the MaxCompiler for finite-difference equation solvers. The experimental results with various settings of architectural design parameters show the best combination of design parameters for pipeline structure can be systematically found by using our models. The effects of changing arithmetic accuracy and using data stream compression are also discussed.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014RCP0013/_p
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@ARTICLE{e98-d_2_298,
author={Keisuke DOHI, Koji OKINA, Rie SOEJIMA, Yuichiro SHIBATA, Kiyoshi OGURI, },
journal={IEICE TRANSACTIONS on Information},
title={Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration},
year={2015},
volume={E98-D},
number={2},
pages={298-308},
abstract={In this paper, we discuss performance modeling of 3-D stencil computing on an FPGA accelerator with a high-level synthesis environment, aiming for efficient exploration of user-space design parameters. First, we analyze resource utilization and performance to formulate these relationships as mathematical models. Then, in order to evaluate our proposed models, we implement heat conduction simulations as a benchmark application, by using MaxCompiler, which is a high-level synthesis tool for FPGAs, and MaxGenFD, which is a domain specific framework of the MaxCompiler for finite-difference equation solvers. The experimental results with various settings of architectural design parameters show the best combination of design parameters for pipeline structure can be systematically found by using our models. The effects of changing arithmetic accuracy and using data stream compression are also discussed.},
keywords={},
doi={10.1587/transinf.2014RCP0013},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration
T2 - IEICE TRANSACTIONS on Information
SP - 298
EP - 308
AU - Keisuke DOHI
AU - Koji OKINA
AU - Rie SOEJIMA
AU - Yuichiro SHIBATA
AU - Kiyoshi OGURI
PY - 2015
DO - 10.1587/transinf.2014RCP0013
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2015
AB - In this paper, we discuss performance modeling of 3-D stencil computing on an FPGA accelerator with a high-level synthesis environment, aiming for efficient exploration of user-space design parameters. First, we analyze resource utilization and performance to formulate these relationships as mathematical models. Then, in order to evaluate our proposed models, we implement heat conduction simulations as a benchmark application, by using MaxCompiler, which is a high-level synthesis tool for FPGAs, and MaxGenFD, which is a domain specific framework of the MaxCompiler for finite-difference equation solvers. The experimental results with various settings of architectural design parameters show the best combination of design parameters for pipeline structure can be systematically found by using our models. The effects of changing arithmetic accuracy and using data stream compression are also discussed.
ER -
English
