IEICE TRANSACTIONS on Information
A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory
Summary :
Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will decline. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts before executing transactions, considering historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 59.2% at a maximum, and 16.8% on average with 16 threads.
- Publication
- IEICE TRANSACTIONS on Information Vol.E99-D No.12 pp.2860-2870
- Publication Date
- 2016/12/01
- Publicized
- 2016/08/24
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2016PAP0006
- Type of Manuscript
- Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
- Category
- Architecture
Authors
Keisuke MASHITA
Nagoya Institute of Technology
Maya TABUCHI
Nagoya Institute of Technology
Ryohei YAMADA
Nagoya Institute of Technology
Tomoaki TSUMURA
Nagoya Institute of Technology
Keyword
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Keisuke MASHITA, Maya TABUCHI, Ryohei YAMADA, Tomoaki TSUMURA, "A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory" in IEICE TRANSACTIONS on Information,
vol. E99-D, no. 12, pp. 2860-2870, December 2016, doi: 10.1587/transinf.2016PAP0006.
Abstract: Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will decline. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts before executing transactions, considering historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 59.2% at a maximum, and 16.8% on average with 16 threads.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2016PAP0006/_p
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@ARTICLE{e99-d_12_2860,
author={Keisuke MASHITA, Maya TABUCHI, Ryohei YAMADA, Tomoaki TSUMURA, },
journal={IEICE TRANSACTIONS on Information},
title={A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory},
year={2016},
volume={E99-D},
number={12},
pages={2860-2870},
abstract={Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will decline. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts before executing transactions, considering historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 59.2% at a maximum, and 16.8% on average with 16 threads.},
keywords={},
doi={10.1587/transinf.2016PAP0006},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory
T2 - IEICE TRANSACTIONS on Information
SP - 2860
EP - 2870
AU - Keisuke MASHITA
AU - Maya TABUCHI
AU - Ryohei YAMADA
AU - Tomoaki TSUMURA
PY - 2016
DO - 10.1587/transinf.2016PAP0006
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E99-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2016
AB - Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will decline. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts before executing transactions, considering historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 59.2% at a maximum, and 16.8% on average with 16 threads.
ER -
English
