IEICE TRANSACTIONS on Information
An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation
Summary :
This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS(255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.
- Publication
- IEICE TRANSACTIONS on Information Vol.E100-D No.12 pp.2953-2961
- Publication Date
- 2017/12/01
- Publicized
- 2017/08/23
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2017EDP7039
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Kentaro KATO
Tsuruoka College
Somsak CHOOMCHUAY
King Monkut's Institute of Technology
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kentaro KATO, Somsak CHOOMCHUAY, "An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation" in IEICE TRANSACTIONS on Information,
vol. E100-D, no. 12, pp. 2953-2961, December 2017, doi: 10.1587/transinf.2017EDP7039.
Abstract: This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS(255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2017EDP7039/_p
Copy
@ARTICLE{e100-d_12_2953,
author={Kentaro KATO, Somsak CHOOMCHUAY, },
journal={IEICE TRANSACTIONS on Information},
title={An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation},
year={2017},
volume={E100-D},
number={12},
pages={2953-2961},
abstract={This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS(255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.},
keywords={},
doi={10.1587/transinf.2017EDP7039},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation
T2 - IEICE TRANSACTIONS on Information
SP - 2953
EP - 2961
AU - Kentaro KATO
AU - Somsak CHOOMCHUAY
PY - 2017
DO - 10.1587/transinf.2017EDP7039
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2017
AB - This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS(255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.
ER -
English
