IEICE TRANSACTIONS on Information
Three Dimensional FPGA Architecture with Fewer TSVs
Summary :
Three-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to offer higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several face-down stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized.
- Publication
- IEICE TRANSACTIONS on Information Vol.E101-D No.2 pp.278-287
- Publication Date
- 2018/02/01
- Publicized
- 2017/11/17
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2017RCP0008
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Device and Architecture
Authors
Motoki AMAGASAKI
Kumamoto University
Masato IKEBE
Kumamoto University
Qian ZHAO
Kumamoto University
Masahiro IIDA
Kumamoto University
Toshinori SUEYOSHI
Kumamoto University
Keyword
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Motoki AMAGASAKI, Masato IKEBE, Qian ZHAO, Masahiro IIDA, Toshinori SUEYOSHI, "Three Dimensional FPGA Architecture with Fewer TSVs" in IEICE TRANSACTIONS on Information,
vol. E101-D, no. 2, pp. 278-287, February 2018, doi: 10.1587/transinf.2017RCP0008.
Abstract: Three-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to offer higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several face-down stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2017RCP0008/_p
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@ARTICLE{e101-d_2_278,
author={Motoki AMAGASAKI, Masato IKEBE, Qian ZHAO, Masahiro IIDA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Information},
title={Three Dimensional FPGA Architecture with Fewer TSVs},
year={2018},
volume={E101-D},
number={2},
pages={278-287},
abstract={Three-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to offer higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several face-down stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized.},
keywords={},
doi={10.1587/transinf.2017RCP0008},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Three Dimensional FPGA Architecture with Fewer TSVs
T2 - IEICE TRANSACTIONS on Information
SP - 278
EP - 287
AU - Motoki AMAGASAKI
AU - Masato IKEBE
AU - Qian ZHAO
AU - Masahiro IIDA
AU - Toshinori SUEYOSHI
PY - 2018
DO - 10.1587/transinf.2017RCP0008
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E101-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2018
AB - Three-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to offer higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several face-down stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized.
ER -
English
