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Wideband Radar Frequency Measurement Receiver Based on FPGA without Mixer
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Summary :
In this letter, a flexible and compatible with fine resolution radar frequency measurement receiver is designed. The receiver is implemented on the platform of Virtex-5 Field Programmable Grid Array (FPGA) from Xilinx. The Digital Down Conversion (DDC) without mixer based on polyphase filter has been successfully introduced in this receiver to obtain lower speed data flow and better resolution. This receiver can adapt to more modulation types and higher density of pulse flow, up to 200000 pulses per second. The measurement results indicate that the receiver is capable of detecting radar pulse signal of 0.2us to 2.5ms width with a major frequency root mean square error (RMSE) within 0.44MHz. Moreover, the wider pulse width and the higher decimation rate of DDC result in better performance. This frequency measurement receiver has been successfully used in a spaceborne radar system.
- Publication
- IEICE TRANSACTIONS on Information Vol.E102-D No.4 pp.859-862
- Publication Date
- 2019/04/01
- Publicized
- 2019/01/18
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2018EDL8161
- Type of Manuscript
- LETTER
- Category
- Computer System
Authors
Xinqun LIU
National University of Defense Technology
Yingxiao ZHAO
National University of Defense Technology
Keyword
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Xinqun LIU, Yingxiao ZHAO, "Wideband Radar Frequency Measurement Receiver Based on FPGA without Mixer" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 4, pp. 859-862, April 2019, doi: 10.1587/transinf.2018EDL8161.
Abstract: In this letter, a flexible and compatible with fine resolution radar frequency measurement receiver is designed. The receiver is implemented on the platform of Virtex-5 Field Programmable Grid Array (FPGA) from Xilinx. The Digital Down Conversion (DDC) without mixer based on polyphase filter has been successfully introduced in this receiver to obtain lower speed data flow and better resolution. This receiver can adapt to more modulation types and higher density of pulse flow, up to 200000 pulses per second. The measurement results indicate that the receiver is capable of detecting radar pulse signal of 0.2us to 2.5ms width with a major frequency root mean square error (RMSE) within 0.44MHz. Moreover, the wider pulse width and the higher decimation rate of DDC result in better performance. This frequency measurement receiver has been successfully used in a spaceborne radar system.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2018EDL8161/_p
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@ARTICLE{e102-d_4_859,
author={Xinqun LIU, Yingxiao ZHAO, },
journal={IEICE TRANSACTIONS on Information},
title={Wideband Radar Frequency Measurement Receiver Based on FPGA without Mixer},
year={2019},
volume={E102-D},
number={4},
pages={859-862},
abstract={In this letter, a flexible and compatible with fine resolution radar frequency measurement receiver is designed. The receiver is implemented on the platform of Virtex-5 Field Programmable Grid Array (FPGA) from Xilinx. The Digital Down Conversion (DDC) without mixer based on polyphase filter has been successfully introduced in this receiver to obtain lower speed data flow and better resolution. This receiver can adapt to more modulation types and higher density of pulse flow, up to 200000 pulses per second. The measurement results indicate that the receiver is capable of detecting radar pulse signal of 0.2us to 2.5ms width with a major frequency root mean square error (RMSE) within 0.44MHz. Moreover, the wider pulse width and the higher decimation rate of DDC result in better performance. This frequency measurement receiver has been successfully used in a spaceborne radar system.},
keywords={},
doi={10.1587/transinf.2018EDL8161},
ISSN={1745-1361},
month={April},}
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TY - JOUR
TI - Wideband Radar Frequency Measurement Receiver Based on FPGA without Mixer
T2 - IEICE TRANSACTIONS on Information
SP - 859
EP - 862
AU - Xinqun LIU
AU - Yingxiao ZHAO
PY - 2019
DO - 10.1587/transinf.2018EDL8161
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2019
AB - In this letter, a flexible and compatible with fine resolution radar frequency measurement receiver is designed. The receiver is implemented on the platform of Virtex-5 Field Programmable Grid Array (FPGA) from Xilinx. The Digital Down Conversion (DDC) without mixer based on polyphase filter has been successfully introduced in this receiver to obtain lower speed data flow and better resolution. This receiver can adapt to more modulation types and higher density of pulse flow, up to 200000 pulses per second. The measurement results indicate that the receiver is capable of detecting radar pulse signal of 0.2us to 2.5ms width with a major frequency root mean square error (RMSE) within 0.44MHz. Moreover, the wider pulse width and the higher decimation rate of DDC result in better performance. This frequency measurement receiver has been successfully used in a spaceborne radar system.
ER -
English
