NVRAM-Aware Mapping Table Management for Flash Storage Devices
Summary :
Flash storage suffers from severe performance degradation due to its inherent internal synchronization overhead. Especially, flushing an L2P (logical address to physical address) mapping table significantly contributes to the performance degradation. To relieve the problem, we propose an efficient L2P mapping table management scheme on the flash storage, which works along with a small-sized NVRAM. It flushes L2P mapping table from DRAM to NVRAM or flash memory selectively. In our experiments, the proposed scheme shows up to 9.37× better performance than conventional schemes.
- Publication
- IEICE TRANSACTIONS on Information Vol.E102-D No.8 pp.1576-1580
- Publication Date
- 2019/08/01
- Publicized
- 2019/04/26
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2019EDL8022
- Type of Manuscript
- LETTER
- Category
- Data Engineering, Web Information Systems
Authors
Yongju SONG
Sungkyunkwan University
Sungkyun LEE
Sungkyunkwan University
Dong Hyun KANG
Dongguk University-Gyeongju
Young Ik EOM
Sungkyunkwan University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yongju SONG, Sungkyun LEE, Dong Hyun KANG, Young Ik EOM, "NVRAM-Aware Mapping Table Management for Flash Storage Devices" in IEICE TRANSACTIONS on Information,
vol. E102-D, no. 8, pp. 1576-1580, August 2019, doi: 10.1587/transinf.2019EDL8022.
Abstract: Flash storage suffers from severe performance degradation due to its inherent internal synchronization overhead. Especially, flushing an L2P (logical address to physical address) mapping table significantly contributes to the performance degradation. To relieve the problem, we propose an efficient L2P mapping table management scheme on the flash storage, which works along with a small-sized NVRAM. It flushes L2P mapping table from DRAM to NVRAM or flash memory selectively. In our experiments, the proposed scheme shows up to 9.37× better performance than conventional schemes.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2019EDL8022/_p
Copy
@ARTICLE{e102-d_8_1576,
author={Yongju SONG, Sungkyun LEE, Dong Hyun KANG, Young Ik EOM, },
journal={IEICE TRANSACTIONS on Information},
title={NVRAM-Aware Mapping Table Management for Flash Storage Devices},
year={2019},
volume={E102-D},
number={8},
pages={1576-1580},
abstract={Flash storage suffers from severe performance degradation due to its inherent internal synchronization overhead. Especially, flushing an L2P (logical address to physical address) mapping table significantly contributes to the performance degradation. To relieve the problem, we propose an efficient L2P mapping table management scheme on the flash storage, which works along with a small-sized NVRAM. It flushes L2P mapping table from DRAM to NVRAM or flash memory selectively. In our experiments, the proposed scheme shows up to 9.37× better performance than conventional schemes.},
keywords={},
doi={10.1587/transinf.2019EDL8022},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - NVRAM-Aware Mapping Table Management for Flash Storage Devices
T2 - IEICE TRANSACTIONS on Information
SP - 1576
EP - 1580
AU - Yongju SONG
AU - Sungkyun LEE
AU - Dong Hyun KANG
AU - Young Ik EOM
PY - 2019
DO - 10.1587/transinf.2019EDL8022
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E102-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2019
AB - Flash storage suffers from severe performance degradation due to its inherent internal synchronization overhead. Especially, flushing an L2P (logical address to physical address) mapping table significantly contributes to the performance degradation. To relieve the problem, we propose an efficient L2P mapping table management scheme on the flash storage, which works along with a small-sized NVRAM. It flushes L2P mapping table from DRAM to NVRAM or flash memory selectively. In our experiments, the proposed scheme shows up to 9.37× better performance than conventional schemes.
ER -
English
