An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm

Keisuke SUGIURA; Hiroki MATSUTANI

doi:10.1587/transinf.2020EDP7174

An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm

Keisuke SUGIURA, Hiroki MATSUTANI

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An efficient hardware implementation for Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. We exploit an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithm to perform scan matching computations for multiple particles in parallel. In the proposed design, several techniques are employed to reduce the resource utilization and to achieve the maximum throughput. Experimental results using the benchmark datasets show that the scan matching is accelerated by 5.31-8.75× and the overall throughput is improved by 3.72-5.10× without seriously degrading the quality of the final outputs. Furthermore, our proposed IP core requires only 44% of the total resources available in the TUL Pynq-Z2 FPGA board, thus facilitating the realization of SLAM applications on indoor mobile robots.

Publication: IEICE TRANSACTIONS on Information Vol.E104-D No.6 pp.789-800

Publication Date: 2021/06/01

Publicized: 2021/03/04

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2020EDP7174

Type of Manuscript: PAPER

Category: Computer System

Authors

Keisuke SUGIURA
Keio University
Hiroki MATSUTANI
Keio University

Keyword

SLAM, GMapping, SoC, FPGA

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Keisuke SUGIURA, Hiroki MATSUTANI, "An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm" in IEICE TRANSACTIONS on Information, vol. E104-D, no. 6, pp. 789-800, June 2021, doi: 10.1587/transinf.2020EDP7174.
Abstract: An efficient hardware implementation for Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. We exploit an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithm to perform scan matching computations for multiple particles in parallel. In the proposed design, several techniques are employed to reduce the resource utilization and to achieve the maximum throughput. Experimental results using the benchmark datasets show that the scan matching is accelerated by 5.31-8.75× and the overall throughput is improved by 3.72-5.10× without seriously degrading the quality of the final outputs. Furthermore, our proposed IP core requires only 44% of the total resources available in the TUL Pynq-Z2 FPGA board, thus facilitating the realization of SLAM applications on indoor mobile robots.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020EDP7174/_p

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@ARTICLE{e104-d_6_789,
author={Keisuke SUGIURA, Hiroki MATSUTANI, },
journal={IEICE TRANSACTIONS on Information},
title={An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm},
year={2021},
volume={E104-D},
number={6},
pages={789-800},
abstract={An efficient hardware implementation for Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. We exploit an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithm to perform scan matching computations for multiple particles in parallel. In the proposed design, several techniques are employed to reduce the resource utilization and to achieve the maximum throughput. Experimental results using the benchmark datasets show that the scan matching is accelerated by 5.31-8.75× and the overall throughput is improved by 3.72-5.10× without seriously degrading the quality of the final outputs. Furthermore, our proposed IP core requires only 44% of the total resources available in the TUL Pynq-Z2 FPGA board, thus facilitating the realization of SLAM applications on indoor mobile robots.},
keywords={},
doi={10.1587/transinf.2020EDP7174},
ISSN={1745-1361},
month={June},}

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TY - JOUR
TI - An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm
T2 - IEICE TRANSACTIONS on Information
SP - 789
EP - 800
AU - Keisuke SUGIURA
AU - Hiroki MATSUTANI
PY - 2021
DO - 10.1587/transinf.2020EDP7174
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E104-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2021
AB - An efficient hardware implementation for Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. We exploit an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithm to perform scan matching computations for multiple particles in parallel. In the proposed design, several techniques are employed to reduce the resource utilization and to achieve the maximum throughput. Experimental results using the benchmark datasets show that the scan matching is accelerated by 5.31-8.75× and the overall throughput is improved by 3.72-5.10× without seriously degrading the quality of the final outputs. Furthermore, our proposed IP core requires only 44% of the total resources available in the TUL Pynq-Z2 FPGA board, thus facilitating the realization of SLAM applications on indoor mobile robots.
ER -