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Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

Daisuke SUZUKI, Takahiro HANYU

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Summary :

A nonvolatile field-programmable gate array (NV-FPGA), where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, an NV-FPGA is proposed where the programmable logic and interconnect function blocks are described in a hardware description language and are pushed through a standard-cell-based design flow with nonvolatile flip-flops. The use of the standard-cell-based design flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical example, the proposed NV-FPGA is designed under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, and the performance of the proposed NV-FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

Publication
IEICE TRANSACTIONS on Information Vol.E104-D No.8 pp.1111-1120
Publication Date
2021/08/01
Publicized
2021/04/16
Online ISSN
1745-1361
DOI
10.1587/transinf.2020LOP0010
Type of Manuscript
Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category
Logic Design

Authors

Daisuke SUZUKI
  University of Aizu
Takahiro HANYU
  Tohoku University

Keyword