IEICE TRANSACTIONS on Information
A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC
Summary :
The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.
- Publication
- IEICE TRANSACTIONS on Information Vol.E105-D No.7 pp.1320-1324
- Publication Date
- 2022/07/01
- Publicized
- 2022/03/25
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2022EDL8002
- Type of Manuscript
- LETTER
- Category
- Computer System
Authors
Qianqian WU
Harbin Institute of Technology
Zhenzhou JI
Harbin Institute of Technology
Keyword
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Qianqian WU, Zhenzhou JI, "A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC" in IEICE TRANSACTIONS on Information,
vol. E105-D, no. 7, pp. 1320-1324, July 2022, doi: 10.1587/transinf.2022EDL8002.
Abstract: The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2022EDL8002/_p
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@ARTICLE{e105-d_7_1320,
author={Qianqian WU, Zhenzhou JI, },
journal={IEICE TRANSACTIONS on Information},
title={A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC},
year={2022},
volume={E105-D},
number={7},
pages={1320-1324},
abstract={The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.},
keywords={},
doi={10.1587/transinf.2022EDL8002},
ISSN={1745-1361},
month={July},}
Copy
TY - JOUR
TI - A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC
T2 - IEICE TRANSACTIONS on Information
SP - 1320
EP - 1324
AU - Qianqian WU
AU - Zhenzhou JI
PY - 2022
DO - 10.1587/transinf.2022EDL8002
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E105-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2022
AB - The shared last level cache (SLLC) in tile chip multiprocessors (TCMP) provides a low off-chip miss rate, but it causes a long on-chip access latency. In the two-level cache hierarchy, data replication stores replicas of L1 victims in the local LLC (L2 cache) to obtain a short local LLC access latency on the next accesses. Many data replication mechanisms have been proposed, but they do not consider both L1 victim reuse behaviors and LLC replica reception capability. They either produce many useless replicas or increase LLC pressure, which limits the improvement of system performance. In this paper, we propose a two-level cache aware adaptive data replication mechanism (TCDR), which controls replication based on both L1 victim reuse behaviors prediction and LLC replica reception capability monitoring. TCDR not only increases the accuracy of L1 replica selection, but also avoids the pressure of replication on LLC. The results show that TCDR improves the system performance with reasonable hardware overhead.
ER -
English
