IEICE TRANSACTIONS on Information
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator
Summary :
This paper presents a design and an implementation of an on-line quality control method for a TRNG (True Random Number Generator) on an FPGA. It is based on a TRNG with RS latches and a temporal XOR corrector, which can make a trade-off between throughput and randomness quality by changing the number of accumulations by XOR. The goal of our method is to increase the throughput within the range of keeping the quality of output random numbers. In order to detect a sign of the loss of quality from the TRNG in parallel with random number generation, our method distinguishes random bitstrings to be tested from those to be output. The test bitstring is generated with the fewer number of accumulations than that of the output bitstring. The number of accumulations will be increased if the test bitstring fails in the randomness test. We designed and evaluated a prototype of on-line quality control system, using a Zynq-7000 FPGA SoC. The results indicate that the TRNG with the proposed method achieved 1.91-2.63 Mbits/s of throughput with 16 latches, following the change of the quality of output random numbers. The total number of logic elements in the prototype system with 16 latches was comparable to an existing system with 256 latches, without quality control capabilities.
- Publication
- IEICE TRANSACTIONS on Information Vol.E106-D No.12 pp.1940-1950
- Publication Date
- 2023/12/01
- Publicized
- 2023/03/24
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2023PAP0001
- Type of Manuscript
- Special Section PAPER (Special Section on Forefront Computing)
- Category
Authors
Naoki FUJIEDA
Aichi Institute of Technology
Shuichi ICHIKAWA
Toyohashi University of Technology
Ryusei OYA
Aichi Institute of Technology
Hitomi KISHIBE
Toyohashi University of Technology
Keyword
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Naoki FUJIEDA, Shuichi ICHIKAWA, Ryusei OYA, Hitomi KISHIBE, "Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator" in IEICE TRANSACTIONS on Information,
vol. E106-D, no. 12, pp. 1940-1950, December 2023, doi: 10.1587/transinf.2023PAP0001.
Abstract: This paper presents a design and an implementation of an on-line quality control method for a TRNG (True Random Number Generator) on an FPGA. It is based on a TRNG with RS latches and a temporal XOR corrector, which can make a trade-off between throughput and randomness quality by changing the number of accumulations by XOR. The goal of our method is to increase the throughput within the range of keeping the quality of output random numbers. In order to detect a sign of the loss of quality from the TRNG in parallel with random number generation, our method distinguishes random bitstrings to be tested from those to be output. The test bitstring is generated with the fewer number of accumulations than that of the output bitstring. The number of accumulations will be increased if the test bitstring fails in the randomness test. We designed and evaluated a prototype of on-line quality control system, using a Zynq-7000 FPGA SoC. The results indicate that the TRNG with the proposed method achieved 1.91-2.63 Mbits/s of throughput with 16 latches, following the change of the quality of output random numbers. The total number of logic elements in the prototype system with 16 latches was comparable to an existing system with 256 latches, without quality control capabilities.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2023PAP0001/_p
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@ARTICLE{e106-d_12_1940,
author={Naoki FUJIEDA, Shuichi ICHIKAWA, Ryusei OYA, Hitomi KISHIBE, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator},
year={2023},
volume={E106-D},
number={12},
pages={1940-1950},
abstract={This paper presents a design and an implementation of an on-line quality control method for a TRNG (True Random Number Generator) on an FPGA. It is based on a TRNG with RS latches and a temporal XOR corrector, which can make a trade-off between throughput and randomness quality by changing the number of accumulations by XOR. The goal of our method is to increase the throughput within the range of keeping the quality of output random numbers. In order to detect a sign of the loss of quality from the TRNG in parallel with random number generation, our method distinguishes random bitstrings to be tested from those to be output. The test bitstring is generated with the fewer number of accumulations than that of the output bitstring. The number of accumulations will be increased if the test bitstring fails in the randomness test. We designed and evaluated a prototype of on-line quality control system, using a Zynq-7000 FPGA SoC. The results indicate that the TRNG with the proposed method achieved 1.91-2.63 Mbits/s of throughput with 16 latches, following the change of the quality of output random numbers. The total number of logic elements in the prototype system with 16 latches was comparable to an existing system with 256 latches, without quality control capabilities.},
keywords={},
doi={10.1587/transinf.2023PAP0001},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator
T2 - IEICE TRANSACTIONS on Information
SP - 1940
EP - 1950
AU - Naoki FUJIEDA
AU - Shuichi ICHIKAWA
AU - Ryusei OYA
AU - Hitomi KISHIBE
PY - 2023
DO - 10.1587/transinf.2023PAP0001
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E106-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2023
AB - This paper presents a design and an implementation of an on-line quality control method for a TRNG (True Random Number Generator) on an FPGA. It is based on a TRNG with RS latches and a temporal XOR corrector, which can make a trade-off between throughput and randomness quality by changing the number of accumulations by XOR. The goal of our method is to increase the throughput within the range of keeping the quality of output random numbers. In order to detect a sign of the loss of quality from the TRNG in parallel with random number generation, our method distinguishes random bitstrings to be tested from those to be output. The test bitstring is generated with the fewer number of accumulations than that of the output bitstring. The number of accumulations will be increased if the test bitstring fails in the randomness test. We designed and evaluated a prototype of on-line quality control system, using a Zynq-7000 FPGA SoC. The results indicate that the TRNG with the proposed method achieved 1.91-2.63 Mbits/s of throughput with 16 latches, following the change of the quality of output random numbers. The total number of logic elements in the prototype system with 16 latches was comparable to an existing system with 256 latches, without quality control capabilities.
ER -
English
