IEICE TRANSACTIONS on Information
High-Speed Low-Complexity Architecture for Reed-Solomon Decoders
Summary :
This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 µm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.
- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.7 pp.1824-1831
- Publication Date
- 2010/07/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E93.D.1824
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Keyword
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Yung-Kuei LU, Ming-Der SHIEH, "High-Speed Low-Complexity Architecture for Reed-Solomon Decoders" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 7, pp. 1824-1831, July 2010, doi: 10.1587/transinf.E93.D.1824.
Abstract: This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 µm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.1824/_p
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@ARTICLE{e93-d_7_1824,
author={Yung-Kuei LU, Ming-Der SHIEH, },
journal={IEICE TRANSACTIONS on Information},
title={High-Speed Low-Complexity Architecture for Reed-Solomon Decoders},
year={2010},
volume={E93-D},
number={7},
pages={1824-1831},
abstract={This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 µm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.},
keywords={},
doi={10.1587/transinf.E93.D.1824},
ISSN={1745-1361},
month={July},}
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TY - JOUR
TI - High-Speed Low-Complexity Architecture for Reed-Solomon Decoders
T2 - IEICE TRANSACTIONS on Information
SP - 1824
EP - 1831
AU - Yung-Kuei LU
AU - Ming-Der SHIEH
PY - 2010
DO - 10.1587/transinf.E93.D.1824
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2010
AB - This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 µm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.
ER -
English
