IEICE TRANSACTIONS on Information
Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor
Summary :
This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.
- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.8 pp.2117-2125
- Publication Date
- 2010/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E93.D.2117
- Type of Manuscript
- Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
- Category
- Application of Multiple-Valued VLSI
Authors
Keyword
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Naofumi HOMMA, Yuichi BABA, Atsushi MIYAMOTO, Takafumi AOKI, "Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2117-2125, August 2010, doi: 10.1587/transinf.E93.D.2117.
Abstract: This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2117/_p
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@ARTICLE{e93-d_8_2117,
author={Naofumi HOMMA, Yuichi BABA, Atsushi MIYAMOTO, Takafumi AOKI, },
journal={IEICE TRANSACTIONS on Information},
title={Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor},
year={2010},
volume={E93-D},
number={8},
pages={2117-2125},
abstract={This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.},
keywords={},
doi={10.1587/transinf.E93.D.2117},
ISSN={1745-1361},
month={August},}
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TY - JOUR
TI - Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor
T2 - IEICE TRANSACTIONS on Information
SP - 2117
EP - 2125
AU - Naofumi HOMMA
AU - Yuichi BABA
AU - Atsushi MIYAMOTO
AU - Takafumi AOKI
PY - 2010
DO - 10.1587/transinf.E93.D.2117
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.
ER -
English
