IEICE TRANSACTIONS on Information
A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
Summary :
This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.
- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.9 pp.2500-2508
- Publication Date
- 2010/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E93.D.2500
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Keyword
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Jeonghun KIM, Suki KIM, Kwang-Hyun BAEK, "A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 9, pp. 2500-2508, September 2010, doi: 10.1587/transinf.E93.D.2500.
Abstract: This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2500/_p
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@ARTICLE{e93-d_9_2500,
author={Jeonghun KIM, Suki KIM, Kwang-Hyun BAEK, },
journal={IEICE TRANSACTIONS on Information},
title={A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform},
year={2010},
volume={E93-D},
number={9},
pages={2500-2508},
abstract={This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.},
keywords={},
doi={10.1587/transinf.E93.D.2500},
ISSN={1745-1361},
month={September},}
Copy
TY - JOUR
TI - A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
T2 - IEICE TRANSACTIONS on Information
SP - 2500
EP - 2508
AU - Jeonghun KIM
AU - Suki KIM
AU - Kwang-Hyun BAEK
PY - 2010
DO - 10.1587/transinf.E93.D.2500
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2010
AB - This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm2 in 0.18 µm CMOS, and the worst-case current of the total chip is 54 mA.
ER -
English
