Testable Critical Path Selection Considering Process Variation

Xiang FU; Huawei LI; Xiaowei LI

doi:10.1587/transinf.E93.D.59

Testable Critical Path Selection Considering Process Variation

Xiang FU, Huawei LI, Xiaowei LI

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Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection.

Publication: IEICE TRANSACTIONS on Information Vol.E93-D No.1 pp.59-67

Publication Date: 2010/01/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E93.D.59

Type of Manuscript: PAPER

Category: Dependable Computing

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Xiang FU, Huawei LI, Xiaowei LI, "Testable Critical Path Selection Considering Process Variation" in IEICE TRANSACTIONS on Information, vol. E93-D, no. 1, pp. 59-67, January 2010, doi: 10.1587/transinf.E93.D.59.
Abstract: Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.59/_p

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@ARTICLE{e93-d_1_59,
author={Xiang FU, Huawei LI, Xiaowei LI, },
journal={IEICE TRANSACTIONS on Information},
title={Testable Critical Path Selection Considering Process Variation},
year={2010},
volume={E93-D},
number={1},
pages={59-67},
abstract={Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection.},
keywords={},
doi={10.1587/transinf.E93.D.59},
ISSN={1745-1361},
month={January},}

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TY - JOUR
TI - Testable Critical Path Selection Considering Process Variation
T2 - IEICE TRANSACTIONS on Information
SP - 59
EP - 67
AU - Xiang FU
AU - Huawei LI
AU - Xiaowei LI
PY - 2010
DO - 10.1587/transinf.E93.D.59
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2010
AB - Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection.
ER -