Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

Guang SUN; Shijun LIN; Depeng JIN; Yong LI; Li SU; Yuanyuan ZHANG; Lieguang ZENG

doi:10.1587/transinf.E94.D.1000

Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

Guang SUN, Shijun LIN, Depeng JIN, Yong LI, Li SU, Yuanyuan ZHANG, Lieguang ZENG

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Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.

Publication: IEICE TRANSACTIONS on Information Vol.E94-D No.5 pp.1000-1007

Publication Date: 2011/05/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E94.D.1000

Type of Manuscript: PAPER

Category: Computer System

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Guang SUN, Shijun LIN, Depeng JIN, Yong LI, Li SU, Yuanyuan ZHANG, Lieguang ZENG, "Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip" in IEICE TRANSACTIONS on Information, vol. E94-D, no. 5, pp. 1000-1007, May 2011, doi: 10.1587/transinf.E94.D.1000.
Abstract: Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.1000/_p

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@ARTICLE{e94-d_5_1000,
author={Guang SUN, Shijun LIN, Depeng JIN, Yong LI, Li SU, Yuanyuan ZHANG, Lieguang ZENG, },
journal={IEICE TRANSACTIONS on Information},
title={Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip},
year={2011},
volume={E94-D},
number={5},
pages={1000-1007},
abstract={Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.},
keywords={},
doi={10.1587/transinf.E94.D.1000},
ISSN={1745-1361},
month={May},}

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TY - JOUR
TI - Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip
T2 - IEICE TRANSACTIONS on Information
SP - 1000
EP - 1007
AU - Guang SUN
AU - Shijun LIN
AU - Depeng JIN
AU - Yong LI
AU - Li SU
AU - Yuanyuan ZHANG
AU - Lieguang ZENG
PY - 2011
DO - 10.1587/transinf.E94.D.1000
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2011
AB - Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.
ER -