IEICE TRANSACTIONS on Information
A Leakage Efficient Instruction TLB Design for Embedded Processors
Summary :
This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.
- Publication
- IEICE TRANSACTIONS on Information Vol.E94-D No.8 pp.1565-1574
- Publication Date
- 2011/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E94.D.1565
- Type of Manuscript
- PAPER
- Category
- Computer System
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Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, "A Leakage Efficient Instruction TLB Design for Embedded Processors" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 8, pp. 1565-1574, August 2011, doi: 10.1587/transinf.E94.D.1565.
Abstract: This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.1565/_p
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@ARTICLE{e94-d_8_1565,
author={Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Leakage Efficient Instruction TLB Design for Embedded Processors},
year={2011},
volume={E94-D},
number={8},
pages={1565-1574},
abstract={This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.},
keywords={},
doi={10.1587/transinf.E94.D.1565},
ISSN={1745-1361},
month={August},}
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TY - JOUR
TI - A Leakage Efficient Instruction TLB Design for Embedded Processors
T2 - IEICE TRANSACTIONS on Information
SP - 1565
EP - 1574
AU - Zhao LEI
AU - Hui XU
AU - Daisuke IKEBUCHI
AU - Tetsuya SUNATA
AU - Mitaro NAMIKI
AU - Hideharu AMANO
PY - 2011
DO - 10.1587/transinf.E94.D.1565
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2011
AB - This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.
ER -
English
