A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones

Md. Nazrul Islam MONDAL; Koji NAKANO; Yasuaki ITO

doi:10.1587/transinf.E94.D.2378

A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones

Md. Nazrul Islam MONDAL, Koji NAKANO, Yasuaki ITO

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Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.

Publication: IEICE TRANSACTIONS on Information Vol.E94-D No.12 pp.2378-2388

Publication Date: 2011/12/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E94.D.2378

Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)

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Md. Nazrul Islam MONDAL, Koji NAKANO, Yasuaki ITO, "A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones" in IEICE TRANSACTIONS on Information, vol. E94-D, no. 12, pp. 2378-2388, December 2011, doi: 10.1587/transinf.E94.D.2378.
Abstract: Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.2378/_p

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@ARTICLE{e94-d_12_2378,
author={Md. Nazrul Islam MONDAL, Koji NAKANO, Yasuaki ITO, },
journal={IEICE TRANSACTIONS on Information},
title={A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones},
year={2011},
volume={E94-D},
number={12},
pages={2378-2388},
abstract={Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.},
keywords={},
doi={10.1587/transinf.E94.D.2378},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones
T2 - IEICE TRANSACTIONS on Information
SP - 2378
EP - 2388
AU - Md. Nazrul Islam MONDAL
AU - Koji NAKANO
AU - Yasuaki ITO
PY - 2011
DO - 10.1587/transinf.E94.D.2378
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2011
AB - Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.
ER -