This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.
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Keivan NAVI, Mohammad ESMAEILDOUST, Amir SABBAGH MOLAHOSSEINI, "A General Reverse Converter Architecture with Low Complexity and High Performance" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 2, pp. 264-273, February 2011, doi: 10.1587/transinf.E94.D.264.
Abstract: This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.264/_p
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@ARTICLE{e94-d_2_264,
author={Keivan NAVI, Mohammad ESMAEILDOUST, Amir SABBAGH MOLAHOSSEINI, },
journal={IEICE TRANSACTIONS on Information},
title={A General Reverse Converter Architecture with Low Complexity and High Performance},
year={2011},
volume={E94-D},
number={2},
pages={264-273},
abstract={This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.},
keywords={},
doi={10.1587/transinf.E94.D.264},
ISSN={1745-1361},
month={February},}
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TY - JOUR
TI - A General Reverse Converter Architecture with Low Complexity and High Performance
T2 - IEICE TRANSACTIONS on Information
SP - 264
EP - 273
AU - Keivan NAVI
AU - Mohammad ESMAEILDOUST
AU - Amir SABBAGH MOLAHOSSEINI
PY - 2011
DO - 10.1587/transinf.E94.D.264
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2011
AB - This paper presents a general architecture for designing efficient reverse converters based on the moduli set {2α, 22β+1-1, 2β-1}, where β < α ≤ 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2α, 22β+1-1, 2β-1} is free from modulo (2k+1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {22n, 22n+1-1, 2n-1} which is a special case of the general set {2α, 22β+1-1, 2β-1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {22n, 22n+1-1, 2n-1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {22n, 22n+1-1, 2n-1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR.
ER -