IEICE TRANSACTIONS on Information
A Leakage Efficient Data TLB Design for Embedded Processors
Summary :
This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
- Publication
- IEICE TRANSACTIONS on Information Vol.E94-D No.1 pp.51-59
- Publication Date
- 2011/01/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E94.D.51
- Type of Manuscript
- PAPER
- Category
- Computer System
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Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, "A Leakage Efficient Data TLB Design for Embedded Processors" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 1, pp. 51-59, January 2011, doi: 10.1587/transinf.E94.D.51.
Abstract: This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.51/_p
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@ARTICLE{e94-d_1_51,
author={Zhao LEI, Hui XU, Daisuke IKEBUCHI, Tetsuya SUNATA, Mitaro NAMIKI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Leakage Efficient Data TLB Design for Embedded Processors},
year={2011},
volume={E94-D},
number={1},
pages={51-59},
abstract={This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.},
keywords={},
doi={10.1587/transinf.E94.D.51},
ISSN={1745-1361},
month={January},}
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TY - JOUR
TI - A Leakage Efficient Data TLB Design for Embedded Processors
T2 - IEICE TRANSACTIONS on Information
SP - 51
EP - 59
AU - Zhao LEI
AU - Hui XU
AU - Daisuke IKEBUCHI
AU - Tetsuya SUNATA
AU - Mitaro NAMIKI
AU - Hideharu AMANO
PY - 2011
DO - 10.1587/transinf.E94.D.51
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2011
AB - This paper presents a leakage efficient data TLB (Translation Look-aside Buffer) design for embedded processors. Due to the data locality in programs, data TLB references tend to hit only a small number of pages during short execution intervals. After dividing the overall execution time into smaller time slices, a leakage reduction mechanism is proposed to detect TLB entries which actually serve for virtual-to-physical address translations within each time slice. Thus, with the integration of the dual voltage supply technique, those TLB entries which are not used for address translations can be put into low leakage mode (with lower voltage supply) to save power. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of a data TLB by 37% on average, with performance degradation less than 0.01%.
ER -
English
