IEICE TRANSACTIONS on Information
Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture
Summary :
Coarse-grained reconfigurable architecture (CGRA) combines the performance of application-specific integrated circuits (ASICs) and the flexibility of general-purpose processors (GPPs), which is a promising solution for embedded systems. With the increasing complexity of reconfigurable resources (processing elements, routing cells, I/O blocks, etc.), the reconfiguration cost is becoming the performance bottleneck. The major reconfiguration cost comes from the frequent memory-read/write operations for transferring the configuration context from main memory to context buffer. To improve the overall performance, it is critical to reduce the amount of configuration context. In this paper, we propose a configuration context reduction method for CGRA. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 71% and speed up the execution up to 68%. The proposed method does not depend on any architectural feature and can be applied to CGRA with an arbitrary architecture.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.335-344
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.335
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Design Methodology
Authors
Keyword
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Shouyi YIN, Chongyong YIN, Leibo LIU, Min ZHU, Shaojun WEI, "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 2, pp. 335-344, February 2012, doi: 10.1587/transinf.E95.D.335.
Abstract: Coarse-grained reconfigurable architecture (CGRA) combines the performance of application-specific integrated circuits (ASICs) and the flexibility of general-purpose processors (GPPs), which is a promising solution for embedded systems. With the increasing complexity of reconfigurable resources (processing elements, routing cells, I/O blocks, etc.), the reconfiguration cost is becoming the performance bottleneck. The major reconfiguration cost comes from the frequent memory-read/write operations for transferring the configuration context from main memory to context buffer. To improve the overall performance, it is critical to reduce the amount of configuration context. In this paper, we propose a configuration context reduction method for CGRA. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 71% and speed up the execution up to 68%. The proposed method does not depend on any architectural feature and can be applied to CGRA with an arbitrary architecture.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.335/_p
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@ARTICLE{e95-d_2_335,
author={Shouyi YIN, Chongyong YIN, Leibo LIU, Min ZHU, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Information},
title={Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture},
year={2012},
volume={E95-D},
number={2},
pages={335-344},
abstract={Coarse-grained reconfigurable architecture (CGRA) combines the performance of application-specific integrated circuits (ASICs) and the flexibility of general-purpose processors (GPPs), which is a promising solution for embedded systems. With the increasing complexity of reconfigurable resources (processing elements, routing cells, I/O blocks, etc.), the reconfiguration cost is becoming the performance bottleneck. The major reconfiguration cost comes from the frequent memory-read/write operations for transferring the configuration context from main memory to context buffer. To improve the overall performance, it is critical to reduce the amount of configuration context. In this paper, we propose a configuration context reduction method for CGRA. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 71% and speed up the execution up to 68%. The proposed method does not depend on any architectural feature and can be applied to CGRA with an arbitrary architecture.},
keywords={},
doi={10.1587/transinf.E95.D.335},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture
T2 - IEICE TRANSACTIONS on Information
SP - 335
EP - 344
AU - Shouyi YIN
AU - Chongyong YIN
AU - Leibo LIU
AU - Min ZHU
AU - Shaojun WEI
PY - 2012
DO - 10.1587/transinf.E95.D.335
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - Coarse-grained reconfigurable architecture (CGRA) combines the performance of application-specific integrated circuits (ASICs) and the flexibility of general-purpose processors (GPPs), which is a promising solution for embedded systems. With the increasing complexity of reconfigurable resources (processing elements, routing cells, I/O blocks, etc.), the reconfiguration cost is becoming the performance bottleneck. The major reconfiguration cost comes from the frequent memory-read/write operations for transferring the configuration context from main memory to context buffer. To improve the overall performance, it is critical to reduce the amount of configuration context. In this paper, we propose a configuration context reduction method for CGRA. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 71% and speed up the execution up to 68%. The proposed method does not depend on any architectural feature and can be applied to CGRA with an arbitrary architecture.
ER -
English
