A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy
Summary :
Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.1 pp.38-45
- Publication Date
- 2012/01/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.38
- Type of Manuscript
- Special Section PAPER (Special Section on Trust, Security and Privacy in Computing and Communication Systems)
- Category
- Trust
Authors
Keyword
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Chao YAN, Hongjun DAI, Tianzhou CHEN, "A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 1, pp. 38-45, January 2012, doi: 10.1587/transinf.E95.D.38.
Abstract: Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.38/_p
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@ARTICLE{e95-d_1_38,
author={Chao YAN, Hongjun DAI, Tianzhou CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy},
year={2012},
volume={E95-D},
number={1},
pages={38-45},
abstract={Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.},
keywords={},
doi={10.1587/transinf.E95.D.38},
ISSN={1745-1361},
month={January},}
Copy
TY - JOUR
TI - A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy
T2 - IEICE TRANSACTIONS on Information
SP - 38
EP - 45
AU - Chao YAN
AU - Hongjun DAI
AU - Tianzhou CHEN
PY - 2012
DO - 10.1587/transinf.E95.D.38
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2012
AB - Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.
ER -
English
