Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption
Summary :
Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.11 pp.2333-2343
- Publication Date
- 2013/11/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.2333
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Yohei HORI
Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)
Toshihiro KATASHITA
Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)
Hirofumi SAKANE
Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)
Kenji TODA
Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)
Akashi SATOH
The University of Electro-Com-mu-ni-ca-tions
Keyword
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Yohei HORI, Toshihiro KATASHITA, Hirofumi SAKANE, Kenji TODA, Akashi SATOH, "Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 11, pp. 2333-2343, November 2013, doi: 10.1587/transinf.E96.D.2333.
Abstract: Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.2333/_p
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@ARTICLE{e96-d_11_2333,
author={Yohei HORI, Toshihiro KATASHITA, Hirofumi SAKANE, Kenji TODA, Akashi SATOH, },
journal={IEICE TRANSACTIONS on Information},
title={Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption},
year={2013},
volume={E96-D},
number={11},
pages={2333-2343},
abstract={Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.},
keywords={},
doi={10.1587/transinf.E96.D.2333},
ISSN={1745-1361},
month={November},}
Copy
TY - JOUR
TI - Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption
T2 - IEICE TRANSACTIONS on Information
SP - 2333
EP - 2343
AU - Yohei HORI
AU - Toshihiro KATASHITA
AU - Hirofumi SAKANE
AU - Kenji TODA
AU - Akashi SATOH
PY - 2013
DO - 10.1587/transinf.E96.D.2333
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2013
AB - Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.
ER -
English
