IEICE TRANSACTIONS on Information
A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures
Summary :
The Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.3 pp.616-623
- Publication Date
- 2013/03/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.616
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Keyword
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Wei GE, Zhi QI, Yue DU, Lu MA, Longxing SHI, "A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 3, pp. 616-623, March 2013, doi: 10.1587/transinf.E96.D.616.
Abstract: The Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.616/_p
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@ARTICLE{e96-d_3_616,
author={Wei GE, Zhi QI, Yue DU, Lu MA, Longxing SHI, },
journal={IEICE TRANSACTIONS on Information},
title={A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures},
year={2013},
volume={E96-D},
number={3},
pages={616-623},
abstract={The Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.},
keywords={},
doi={10.1587/transinf.E96.D.616},
ISSN={1745-1361},
month={March},}
Copy
TY - JOUR
TI - A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures
T2 - IEICE TRANSACTIONS on Information
SP - 616
EP - 623
AU - Wei GE
AU - Zhi QI
AU - Yue DU
AU - Lu MA
AU - Longxing SHI
PY - 2013
DO - 10.1587/transinf.E96.D.616
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2013
AB - The Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.
ER -
English
