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Hyuk-Jun LEE, Seung-Chul KIM, Eui-Young CHUNG, "A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 4, pp. 963-966, April 2013, doi: 10.1587/transinf.E96.D.963.
Abstract: A packet memory stores packets in internet routers and it requires typically RTTC for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to , where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.963/_p
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@ARTICLE{e96-d_4_963,
author={Hyuk-Jun LEE, Seung-Chul KIM, Eui-Young CHUNG, },
journal={IEICE TRANSACTIONS on Information},
title={A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method},
year={2013},
volume={E96-D},
number={4},
pages={963-966},
abstract={A packet memory stores packets in internet routers and it requires typically RTTC for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to , where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.},
keywords={},
doi={10.1587/transinf.E96.D.963},
ISSN={1745-1361},
month={April},}
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TY - JOUR
TI - A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method
T2 - IEICE TRANSACTIONS on Information
SP - 963
EP - 966
AU - Hyuk-Jun LEE
AU - Seung-Chul KIM
AU - Eui-Young CHUNG
PY - 2013
DO - 10.1587/transinf.E96.D.963
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2013
AB - A packet memory stores packets in internet routers and it requires typically RTTC for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router's output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heavily limited by power and heat problems. Previous work shows the packet memory size can be reduced to , where N is the number of long-lived TCP flows. In this paper, we propose a novel packet memory architecture which splits the packet memory into on-chip and off-chip packet memories. We also propose a low-power packet mapping method for this architecture by estimating the latency of packets and mapping packets with small latencies to the on-chip memory. The experimental results show that our proposed architecture and mapping method reduce the dynamic power consumption of the off-chip memory by as much as 94.1% with only 50% of the packet buffer size suggested by the previous work in realistic scenarios.
ER -
English
