This paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.
Agus BEJO
Tokyo Institute of Technology
Dongju LI
Tokyo Institute of Technology
Tsuyoshi ISSHIKI
Tokyo Institute of Technology
Hiroaki KUNIEDA
Tokyo Institute of Technology
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Agus BEJO, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, "Retargeting Derivative-ASIP with Assembly Converter Tool" in IEICE TRANSACTIONS on Information,
vol. E97-D, no. 5, pp. 1188-1195, May 2014, doi: 10.1587/transinf.E97.D.1188.
Abstract: This paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E97.D.1188/_p
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@ARTICLE{e97-d_5_1188,
author={Agus BEJO, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Information},
title={Retargeting Derivative-ASIP with Assembly Converter Tool},
year={2014},
volume={E97-D},
number={5},
pages={1188-1195},
abstract={This paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.},
keywords={},
doi={10.1587/transinf.E97.D.1188},
ISSN={1745-1361},
month={May},}
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TY - JOUR
TI - Retargeting Derivative-ASIP with Assembly Converter Tool
T2 - IEICE TRANSACTIONS on Information
SP - 1188
EP - 1195
AU - Agus BEJO
AU - Dongju LI
AU - Tsuyoshi ISSHIKI
AU - Hiroaki KUNIEDA
PY - 2014
DO - 10.1587/transinf.E97.D.1188
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2014
AB - This paper firstly presents a processor design with Derivative ASIP approach. The architecture of processor is designed by making use of a well-known embedded processor's instruction-set as a base architecture. To improve its performance, the architecture is enhanced with more hardware resources such as registers, interfaces and instruction extensions which might achieve target specifications. Secondly, a new approach for retargeting compiler by means of assembly converter tool is proposed. Our retargeting approach is practical because it is performed by the assembly converter tool with a simple configuration file and independent from a base compiler. With our proposed approach, both architecture flexibility and a good quality of assembly code can be obtained at once. Compared to other compilers, experiments show that our approach capable of generating code as high efficiency as its base compiler and the developed ASIP results in better performance than its base processor.
ER -