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[Author] Akinobu SATOH(1hit)

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  • Interconnection of Stacked Layers by Bumpless Wiring in Wafer-Level Three-Dimensional Device

    Akinobu SATOH  

     
    PAPER

      Vol:
    E84-C No:12
      Page(s):
    1746-1755

    This paper describes the wafer-level, three-dimensional packaging for MEMS in which sensors, actuators, electronic circuits and other functions are combined together in one integrated block. Si wafers with built-in MEMS functions were integrated with no change in thickness to ensure mechanical strength and improve heat dissipation. In the entire process of three-dimensional integration, Si wafers were processed at temperatures below 400C to prevent degradation of their built-in functions. A description is made of the low-temperature oxidation technology developed by us, which makes through-holes of high density and high aspect ratio in Si wafers with built-in functions by the Optical Excitation Electropolishing Method (OEEM) and forms an oxide film on the hole walls simply by replacing electrolyte. Next, a description is presented of the bumpless interconnection method which fills through-holes of stacked layers with metal by the molten metal suction method and of the electrocapillary effect as a countermeasure to prevent the filler metal from dropping out of holes under its own weight.