Interconnection of Stacked Layers by Bumpless Wiring in Wafer-Level Three-Dimensional Device

Akinobu SATOH

Interconnection of Stacked Layers by Bumpless Wiring in Wafer-Level Three-Dimensional Device

Akinobu SATOH

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This paper describes the wafer-level, three-dimensional packaging for MEMS in which sensors, actuators, electronic circuits and other functions are combined together in one integrated block. Si wafers with built-in MEMS functions were integrated with no change in thickness to ensure mechanical strength and improve heat dissipation. In the entire process of three-dimensional integration, Si wafers were processed at temperatures below 400C to prevent degradation of their built-in functions. A description is made of the low-temperature oxidation technology developed by us, which makes through-holes of high density and high aspect ratio in Si wafers with built-in functions by the Optical Excitation Electropolishing Method (OEEM) and forms an oxide film on the hole walls simply by replacing electrolyte. Next, a description is presented of the bumpless interconnection method which fills through-holes of stacked layers with metal by the molten metal suction method and of the electrocapillary effect as a countermeasure to prevent the filler metal from dropping out of holes under its own weight.

Publication: IEICE TRANSACTIONS on Electronics Vol.E84-C No.12 pp.1746-1755

Publication Date: 2001/12/01

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Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts)

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Akinobu SATOH, "Interconnection of Stacked Layers by Bumpless Wiring in Wafer-Level Three-Dimensional Device" in IEICE TRANSACTIONS on Electronics, vol. E84-C, no. 12, pp. 1746-1755, December 2001, doi: .
Abstract: This paper describes the wafer-level, three-dimensional packaging for MEMS in which sensors, actuators, electronic circuits and other functions are combined together in one integrated block. Si wafers with built-in MEMS functions were integrated with no change in thickness to ensure mechanical strength and improve heat dissipation. In the entire process of three-dimensional integration, Si wafers were processed at temperatures below 400C to prevent degradation of their built-in functions. A description is made of the low-temperature oxidation technology developed by us, which makes through-holes of high density and high aspect ratio in Si wafers with built-in functions by the Optical Excitation Electropolishing Method (OEEM) and forms an oxide film on the hole walls simply by replacing electrolyte. Next, a description is presented of the bumpless interconnection method which fills through-holes of stacked layers with metal by the molten metal suction method and of the electrocapillary effect as a countermeasure to prevent the filler metal from dropping out of holes under its own weight.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_12_1746/_p

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@ARTICLE{e84-c_12_1746,
author={Akinobu SATOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Interconnection of Stacked Layers by Bumpless Wiring in Wafer-Level Three-Dimensional Device},
year={2001},
volume={E84-C},
number={12},
pages={1746-1755},
abstract={This paper describes the wafer-level, three-dimensional packaging for MEMS in which sensors, actuators, electronic circuits and other functions are combined together in one integrated block. Si wafers with built-in MEMS functions were integrated with no change in thickness to ensure mechanical strength and improve heat dissipation. In the entire process of three-dimensional integration, Si wafers were processed at temperatures below 400C to prevent degradation of their built-in functions. A description is made of the low-temperature oxidation technology developed by us, which makes through-holes of high density and high aspect ratio in Si wafers with built-in functions by the Optical Excitation Electropolishing Method (OEEM) and forms an oxide film on the hole walls simply by replacing electrolyte. Next, a description is presented of the bumpless interconnection method which fills through-holes of stacked layers with metal by the molten metal suction method and of the electrocapillary effect as a countermeasure to prevent the filler metal from dropping out of holes under its own weight.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Interconnection of Stacked Layers by Bumpless Wiring in Wafer-Level Three-Dimensional Device
T2 - IEICE TRANSACTIONS on Electronics
SP - 1746
EP - 1755
AU - Akinobu SATOH
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2001
AB - This paper describes the wafer-level, three-dimensional packaging for MEMS in which sensors, actuators, electronic circuits and other functions are combined together in one integrated block. Si wafers with built-in MEMS functions were integrated with no change in thickness to ensure mechanical strength and improve heat dissipation. In the entire process of three-dimensional integration, Si wafers were processed at temperatures below 400C to prevent degradation of their built-in functions. A description is made of the low-temperature oxidation technology developed by us, which makes through-holes of high density and high aspect ratio in Si wafers with built-in functions by the Optical Excitation Electropolishing Method (OEEM) and forms an oxide film on the hole walls simply by replacing electrolyte. Next, a description is presented of the bumpless interconnection method which fills through-holes of stacked layers with metal by the molten metal suction method and of the electrocapillary effect as a countermeasure to prevent the filler metal from dropping out of holes under its own weight.
ER -