A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.