A Decision Circuit with Phase Detectors for 10-Gb/s Optical Communication Systems
Summary :
A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.4 pp.496-502
- Publication Date
- 1996/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
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Makoto SHIKATA, Akira NISHINO, Ryoji SHIGEMASA, Tamotsu KIMURA, Takashi USHIKUBO, "A Decision Circuit with Phase Detectors for 10-Gb/s Optical Communication Systems" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 4, pp. 496-502, April 1996, doi: .
Abstract: A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_4_496/_p
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@ARTICLE{e79-c_4_496,
author={Makoto SHIKATA, Akira NISHINO, Ryoji SHIGEMASA, Tamotsu KIMURA, Takashi USHIKUBO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Decision Circuit with Phase Detectors for 10-Gb/s Optical Communication Systems},
year={1996},
volume={E79-C},
number={4},
pages={496-502},
abstract={A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A Decision Circuit with Phase Detectors for 10-Gb/s Optical Communication Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 496
EP - 502
AU - Makoto SHIKATA
AU - Akira NISHINO
AU - Ryoji SHIGEMASA
AU - Tamotsu KIMURA
AU - Takashi USHIKUBO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1996
AB - A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.
ER -
English
