Classical studies of Asynchronous Transfer Mode (ATM) switching elements and in particular the buffer behavior of the Shared Buffer Memory (SBM), assume that all read and write operations of cells to, respectively from, the SBM are executed simultaneously. However, in a real switching element, the inlets (outlets) are scanned sequentially for arriving (departing) cells during the so-called input (output) cycle. Furthermore, the input and output cycles are intermingled, each read operation being followed by a write operation. This is referred to as the Timeslot Interchange Mechanism (TIM). In this paper, we present the analysis of a queueing model that includes the TIM. We model the cell arrival processes on the inlets of the switching element as independent Bernoulli arrival processes. Moreover, we assume that cells are routed from the inlets to the outlets of the switching element according to an independent and uniform process, i.e., the destinations of consecutive cell arrivals on any given inlet are independent and for a given cell all destinations are equiprobable. Under these assumptions, we will derive expressions for the probability generating functions of the queue length in an individual routing group (a logical queue that contains all cells scheduled for the same destination), the (total) queue length in the SBM, and the cell waiting time. From these results, expressions for the mean values and the tail distributions of these quantities are calculated, and the influence of the TIM on the buffer behavior is studied through comparison with a model where all read and write operations occur simultaneously.

In this Letter, we investigate the loss performance of a discrete-time single-server queueing system with periodic vacations, with which we are often confronted in traffic control, such as cell scheduling or priority control schemes, at ATM nodes. Explicit expressions are derived for the cell loss ratio in terms of the distribution of the buffer contents in an infinite capacity queue.