Classical studies of Asynchronous Transfer Mode (ATM) switching elements and in particular the buffer behavior of the Shared Buffer Memory (SBM), assume that all read and write operations of cells to, respectively from, the SBM are executed simultaneously. However, in a real switching element, the inlets (outlets) are scanned sequentially for arriving (departing) cells during the so-called input (output) cycle. Furthermore, the input and output cycles are intermingled, each read operation being followed by a write operation. This is referred to as the Timeslot Interchange Mechanism (TIM). In this paper, we present the analysis of a queueing model that includes the TIM. We model the cell arrival processes on the inlets of the switching element as independent Bernoulli arrival processes. Moreover, we assume that cells are routed from the inlets to the outlets of the switching element according to an independent and uniform process, i.e., the destinations of consecutive cell arrivals on any given inlet are independent and for a given cell all destinations are equiprobable. Under these assumptions, we will derive expressions for the probability generating functions of the queue length in an individual routing group (a logical queue that contains all cells scheduled for the same destination), the (total) queue length in the SBM, and the cell waiting time. From these results, expressions for the mean values and the tail distributions of these quantities are calculated, and the influence of the TIM on the buffer behavior is studied through comparison with a model where all read and write operations occur simultaneously.
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Bart de SCHEPPER, Bart STEYAERT, Sabine WITTEVRONGEL, Herwig BRUNEEL, "Influence of the Timeslot Interchange Mechanism on the Buffer Behavior of an Integrated Switching Element" in IEICE TRANSACTIONS on Communications,
vol. E87-B, no. 4, pp. 909-917, April 2004, doi: .
Abstract: Classical studies of Asynchronous Transfer Mode (ATM) switching elements and in particular the buffer behavior of the Shared Buffer Memory (SBM), assume that all read and write operations of cells to, respectively from, the SBM are executed simultaneously. However, in a real switching element, the inlets (outlets) are scanned sequentially for arriving (departing) cells during the so-called input (output) cycle. Furthermore, the input and output cycles are intermingled, each read operation being followed by a write operation. This is referred to as the Timeslot Interchange Mechanism (TIM). In this paper, we present the analysis of a queueing model that includes the TIM. We model the cell arrival processes on the inlets of the switching element as independent Bernoulli arrival processes. Moreover, we assume that cells are routed from the inlets to the outlets of the switching element according to an independent and uniform process, i.e., the destinations of consecutive cell arrivals on any given inlet are independent and for a given cell all destinations are equiprobable. Under these assumptions, we will derive expressions for the probability generating functions of the queue length in an individual routing group (a logical queue that contains all cells scheduled for the same destination), the (total) queue length in the SBM, and the cell waiting time. From these results, expressions for the mean values and the tail distributions of these quantities are calculated, and the influence of the TIM on the buffer behavior is studied through comparison with a model where all read and write operations occur simultaneously.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e87-b_4_909/_p
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@ARTICLE{e87-b_4_909,
author={Bart de SCHEPPER, Bart STEYAERT, Sabine WITTEVRONGEL, Herwig BRUNEEL, },
journal={IEICE TRANSACTIONS on Communications},
title={Influence of the Timeslot Interchange Mechanism on the Buffer Behavior of an Integrated Switching Element},
year={2004},
volume={E87-B},
number={4},
pages={909-917},
abstract={Classical studies of Asynchronous Transfer Mode (ATM) switching elements and in particular the buffer behavior of the Shared Buffer Memory (SBM), assume that all read and write operations of cells to, respectively from, the SBM are executed simultaneously. However, in a real switching element, the inlets (outlets) are scanned sequentially for arriving (departing) cells during the so-called input (output) cycle. Furthermore, the input and output cycles are intermingled, each read operation being followed by a write operation. This is referred to as the Timeslot Interchange Mechanism (TIM). In this paper, we present the analysis of a queueing model that includes the TIM. We model the cell arrival processes on the inlets of the switching element as independent Bernoulli arrival processes. Moreover, we assume that cells are routed from the inlets to the outlets of the switching element according to an independent and uniform process, i.e., the destinations of consecutive cell arrivals on any given inlet are independent and for a given cell all destinations are equiprobable. Under these assumptions, we will derive expressions for the probability generating functions of the queue length in an individual routing group (a logical queue that contains all cells scheduled for the same destination), the (total) queue length in the SBM, and the cell waiting time. From these results, expressions for the mean values and the tail distributions of these quantities are calculated, and the influence of the TIM on the buffer behavior is studied through comparison with a model where all read and write operations occur simultaneously.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Influence of the Timeslot Interchange Mechanism on the Buffer Behavior of an Integrated Switching Element
T2 - IEICE TRANSACTIONS on Communications
SP - 909
EP - 917
AU - Bart de SCHEPPER
AU - Bart STEYAERT
AU - Sabine WITTEVRONGEL
AU - Herwig BRUNEEL
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E87-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2004
AB - Classical studies of Asynchronous Transfer Mode (ATM) switching elements and in particular the buffer behavior of the Shared Buffer Memory (SBM), assume that all read and write operations of cells to, respectively from, the SBM are executed simultaneously. However, in a real switching element, the inlets (outlets) are scanned sequentially for arriving (departing) cells during the so-called input (output) cycle. Furthermore, the input and output cycles are intermingled, each read operation being followed by a write operation. This is referred to as the Timeslot Interchange Mechanism (TIM). In this paper, we present the analysis of a queueing model that includes the TIM. We model the cell arrival processes on the inlets of the switching element as independent Bernoulli arrival processes. Moreover, we assume that cells are routed from the inlets to the outlets of the switching element according to an independent and uniform process, i.e., the destinations of consecutive cell arrivals on any given inlet are independent and for a given cell all destinations are equiprobable. Under these assumptions, we will derive expressions for the probability generating functions of the queue length in an individual routing group (a logical queue that contains all cells scheduled for the same destination), the (total) queue length in the SBM, and the cell waiting time. From these results, expressions for the mean values and the tail distributions of these quantities are calculated, and the influence of the TIM on the buffer behavior is studied through comparison with a model where all read and write operations occur simultaneously.
ER -