A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired non-homogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of non-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates favorable results for Xilinx XC4000 CLBs. Over a set of MCNC benchmarks, our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.

This paper presents an efficient queue manager chip for controlling a 16 16 shared buffer ATM switch with a 256-cell buffer. Compared to conventional implementations of queue managers for shared buffer ATM switches, our design eliminates the idle address FIFO and the pre-allocated bubbles at the tails of output queues. The former reduces the storage size required for queue management, while the latter improves the effective buffer capacity. Such modular implementation also provides flexibilities in queue management implementation. Back-pressure with soft-full and hard-full flow control for multi-stage expansion and two priority classes with push-out cell discarding are supported without extra hardware overhead. This chip was designed and fabricated using 0.8µm CMOS technology. It has 35,700 transistors in a chip area of 28.3mm2, with a core of 10.4mm2and 32,960 transistors. Two test sequences were developed during the design phase to fully verify the queue management functions of the prototype chip. The queue manager chip was tested up to 36 MHz, and is able to control a 16 16 shared buffer switch with a 155 MHz link rate.

A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures, consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for larger circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% fewer CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2,79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.

Multicast ATM switches are essential to support various types of services in the Broadband ISDN. In this paper we present an efficient architecture to support multicasting in shared buffer ATM switches. A lookahead technique is employed to resolve the head-of-line blocking problem in the multicast-queue approach, thus improving the throughput of the multicast traffic. The arbitration between multicast and unicast services is investigated to prevent the lookahead technique from increasing the multicast dominance. We show through performance and complexity comparisons that with a small hardware overhead over the multicast-queue approach, our architecture provides a throughput performance comparable to address-duplication or searchable-queue-based approaches.